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| Preliminary User's Manual PD780828A Subseries 8-bit Single-Chip Microcontroller PD780824A PD780826A PD780828A PD78F0828A Document No. U16504EE1V1UD00 Date Published January 2003 NEC Corporation 2003 Printed in Germany NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 2 User's Manual U16504EE1V1UD00 * The information in this document is current as of 28.01, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC Electronics no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". * * * * * The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "Special": "Specific": The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics 's willingness to support a given application. Notes: 1. 2. " NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. " NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02.10 User's Manual U16504EE1V1UD00 3 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327 Sucursal en Espana Madrid, Spain Tel: 091- 504 27 87 Fax: 091- 504 28 60 Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 Branch Sweden Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Singapore Pte. Ltd. Singapore Tel: 65-6253-8311 Fax: 65-6250-3583 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos, Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 4 User's Manual U16504EE1V1UD00 Preface Readers This manual has been prepared for engineers who want to understand the functions of the PD780828A Subseries and design and develop its application systems and programs. PD780828A Subseries: PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A), PD780824A(A1), PD780826A(A1), PD780828A(A1), PD780824A(A2), PD780826A(A2), PD780828A(A2) Purpose This manual is intended for users to understand the functions of the PD780828A Subseries. The PD780828A subseries manual is separated into two parts: this manual and the instruction edition (common to the 78K/0 series). Organization PD780828A Subseries This Manual 78K/0 series User's Manual Instruction * * * * Pin functions Internal block functions Interrupt Other on-chip peripheral functions * CPU functions * Instruction set * Explanation of each instruction How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. * When you want to use this manual as the manual for (A) products, (A1) products, and (A2) products: Only the quality grade differs between (A), (A1) and (A2) products. Read the part number as follows: PD780824A PD780824A(A), PD780824A(A1), PD780824A(A2) PD780826A PD780826A(A), PD780826A(A1), PD780826A(A2) PD780828A PD780828A(A), PD780828A(A1), PD780828A(A2) PD78F0828A PD78F0828A(A) * When you want to understand the function in general: Read this manual in the order of the contents. * How to interpret the register format: For the bit number enclosed in square, the bit name is defined as a reserved word in RA78K/0, and in CC78K/0 and defined in the header file of hte IAR compiler. * To make sure the details of the registers when you know the register name. Refer to Appendix C. User's Manual U16504EE1V1UD00 5 Preface Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. * Related documents for PD780828A Subseries Document name PD780828A Subseries User's Manual 78K/0 Series User's Manual-Instruction 78K/0 Series Instruction Table 78K/0 Series Instruction Set Document No. Japanese Planned IEU-849 U10903J U10904J English U16387E U12326E - * Related documents for development tools (User's Manuals) Document name Operation Language Document No. Japanese EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 U11517J U11518J EEA-618 EEU-777 U14889J Planned Reference External part user open Interface Guide U15373J U15802J U15185J English EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEA-1208 U14889E U13357E U15373E U15802E U15185E RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation Language Operation Language Programming Note CC78K/0 C Compiler CC78K/0 C Compiler Application Note CC78K Series Library Source File IE-78K0-NS-A IE-78K0-NS-P04 IE-780828-NS-EM4 NP-80GC-TQ SM78K0 System Simulator WindowsTM Base SM78K0 Series System Simulator ID78K0-NS Integrated Debugger Windows Base 6 User's Manual U16504EE1V1UD00 Preface * Related documents for embedded software (User's Manual) Document name Basics 78K/0 Series Real-Time OS Installation Technical 78K/0 Series OS MX78K0 Fuzzy Knowledge Data Creation Tool Basics Document No. Japanese U11537J U11536J U11538J EEU-5010 EEU-829 EEU1438 EEU-1444 EEU-1441 EEU-1458 English 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support SysEEU-862 tem-Translator 78K/0 Series Fuzzy Inference Development Support System- Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System- Fuzzy Inference Debugger EEU-858 EEU-921 * Other Documents Document name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices Reliability Quality Control on NEC Semiconductor Devices Electric Static Discharge (ESD) Test Semiconductor Devices Quality Assurance Guide Microcontroller Related Product Guide - Third Party Manufacturers Document No. Japanese C10943X C10535J C11531J C10983J MEM-539 MEI-603 U11416J C10535E C11531E C10983E MEI-1202 English Caution: The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design. User's Manual U16504EE1V1UD00 7 Preface Legend Symbols and notation are used as follows: Weight in data notation : Left is high-order column, right is low order column Active low notation : xxx (pin or signal name is over-scored) or /xxx (slash before signal name) Memory map address: : High order at high stage and low order at low stage Note Caution Remark Numeric notation : Explanation of (Note) in the text : Item deserving extra attention : Supplementary explanation to the text : Binary . . . XXXX or XXXB Decimal . . . XXXX Hexadecimal . . . XXXXH or 0x XXXX Prefixes representing powers of 2 (address space, memory capacity) K (kilo) : 210 = 1024 M (mega) : 220 = 10242 = 1,048,576 G (giga) : 230 = 10243 = 1,073,741,824 8 User's Manual U16504EE1V1UD00 Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Outline (PD780828A Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Quality Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 78K/0 Series Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Overview of Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Differences between Flash and Mask ROM version . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Chapter 2 2.1 2.2 2.3 Pin Function (PD780828A Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin Function List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Non-Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Description of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.1 P00 to P03 (Port 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.2 P10 to P14 (Port 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.3 P20 to P27 (Port 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.4 P34 to P37 (Port 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.5 P40 to P47 (Port 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.6 P50 to P57 (Port 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.7 P60 to P65 (Port 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.8 P80 to P87 (Port 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3.9 P90 to P97 (Port 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3.10 CTXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.11 CRXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.12 CCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.13 COM0 to COM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.14 VLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.15 AVDD / AVREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.16 AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.17 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.18 X1 and X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.19 SMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.20 SMVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.21 VDD0, VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3.22 VSS0, VSS1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3.23 VPP (PD78F0828A only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3.24 IC (Mask ROM version only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins . . . . . . . . . . . . . . . 45 Chapter 3 3.1 CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.1 Internal program memory space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.1.2 Internal data memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.3 Special function register (SFR) area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.4 Data memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2 Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.2.1 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.2.2 General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.3 Special function register (SFR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3 Instruction Address Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.3.1 Relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 User's Manual U16504EE1V1UD00 9 3.3.2 Immediate addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.3.3 Table indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.4 Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.4 Operand Address Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.4.1 Implied addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.4.2 Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.4.3 Direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.4.4 Short direct addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.4.5 Special function register (SFR) addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.4.6 Register indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.4.7 Based addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.4.8 Based indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.4.9 Stack addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Chapter 4 4.1 4.2 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.2.1 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.2.2 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.3 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.2.4 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.2.5 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.2.6 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.7 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.8 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.2.9 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3 Port Function Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.4 Port Function Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.1 Writing to input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.2 Reading from input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.3 Operations on input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Chapter 5 5.1 5.2 5.3 5.4 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Clock Generator Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Clock Generator Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Clock Generator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 System Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.1 Main system clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.5 Clock Generator Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.6 Changing System Clock and CPU Clock Settings . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.6.1 Time required for switchover between system clock and CPU clock . . . . . . . . 110 5.6.2 System clock and CPU clock switching procedure . . . . . . . . . . . . . . . . . . . . . . 111 Chapter 6 6.1 6.2 6.3 6.4 16-Bit Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 16-Bit Timer 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 16-Bit Timer 2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16-Bit Timer 2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16-Bit Timer 2 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.4.1 Pulse width measurement operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.5 16-Bit Timer 2 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Chapter 7 7.1 8-Bit Timer/Event Counters 50 and 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8-Bit Timer/Event Counters 50 and 51 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.1.1 8-bit operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.1.2 16-bit operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.2 8-Bit Timer/Event Counters 50 and 51 Configurations. . . . . . . . . . . . . . . . . . . . . . . 129 7.3 8-Bit Timer/Event Counters 50 and 51 Control Registers . . . . . . . . . . . . . . . . . . . . 132 7.4 8-Bit Timer/Event Counters 50 and 51 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10 User's Manual U16504EE1V1UD00 7.4.1 Interval timer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.4.2 External event counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.4.3 Square-wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.4.4 PWM output operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7.5 Operation as interval timer (16-bit operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7.6 Cautions on 8-Bit Timer/Event Counters 50 and 51 . . . . . . . . . . . . . . . . . . . . . . . . . 153 Chapter 8 8.1 8.2 8.3 8.4 8-Bit Timer 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8-Bit Timer 52 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8-Bit Timer 52 Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8-Bit Timer 52 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 8-Bit Timer 52 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.4.1 Interval timer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Chapter 9 9.1 9.2 9.3 9.4 Watch Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Watch Timer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Watch Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Watch Timer Mode Register (WTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Watch Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.4.1 Watch timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.4.2 Interval timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Chapter 10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.1 10.2 10.3 10.4 Watchdog Timer Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Watchdog Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Watchdog Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 10.4.1 Watchdog timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 10.4.2 Interval timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Chapter 11 Clock Output Control Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.1 11.2 11.3 Clock Output Control Circuit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Clock Output Control Circuit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Clock Output Function Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Chapter 12 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 12.1 12.2 12.3 12.4 A/D Converter Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 A/D Converter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 A/D Converter Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 A/D Converter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.4.1 Basic Operations of A/D Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.4.2 Input voltage and conversion results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.4.3 A/D converter operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.5 A/D Converter Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.6 Cautions on Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.6.1 D/A converter mode register (DAM0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Chapter 13 Serial Interface SIO30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 13.1 13.2 13.3 13.4 13.5 SIO30 Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SIO30 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 List of SFRs (Special Function Registers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Serial Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Serial Interface Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 13.5.1 Operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 13.5.2 Three-wire serial I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Chapter 14 Serial Interface SIO31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.1 SIO31 Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 User's Manual U16504EE1V1UD00 11 14.2 14.3 14.4 14.5 SIO31 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 List of SFRs (Special Function Registers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Serial Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Serial Interface Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.5.1 Operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.5.2 Three-wire serial I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 14.5.3 Two-wire serial I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Chapter 15 Serial Interface Channel UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.1 15.2 15.3 15.4 15.5 UART Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 UART Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 List of SFRS (Special Function Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Serial Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Serial Interface Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.5.1 Operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.5.2 Asynchronous serial interface (UART) mode . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.6 Behavior of UART during Standby of the Controller . . . . . . . . . . . . . . . . . . . . . . . . 238 Chapter 16 CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.1 CAN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.1.1 Protocol Mode Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.1.2 Message Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.1.3 Data Frame / Remote Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 16.1.4 Description of each field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.1.5 Error Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 16.1.6 Overload Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 16.2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.2.1 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.2.2 Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.2.3 Multi Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.2.4 Multi Cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.2.5 Sleep Mode/Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.2.6 Error Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.2.7 Baud Rate Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 16.2.8 State Shift Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 16.3 Outline Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 16.4 Connection with Target System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.5 CAN Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.6 Special Function Register for CAN-module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 16.7 Message and Buffer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 16.8 Transmit Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 16.9 Transmit Message Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 16.10 Receive Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 16.11 Receive Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.12 Mask Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 16.13 Operation of the CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.13.1 CAN control register (CANC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.13.2 DCAN Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.13.3 CAN Transmit Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.13.4 CAN Receive Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.13.5 Message Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 16.14 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.15 Function Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 16.15.1 Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 16.15.2 Receive Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 16.15.3 Mask Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.15.4 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.16 Interrupt Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 User's Manual U16504EE1V1UD00 12 16.16.1 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.16.2 Transmit Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.16.3 Receive Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.16.4 Error Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 16.17 Influence of the standby Function of the CAN Controller . . . . . . . . . . . . . . . . . . . . 306 16.17.1 CPU Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 16.17.2 CPU Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 16.17.3 DCAN Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 16.17.4 DCAN Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 16.18 Functional Description by Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 16.18.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 16.18.2 Transmit Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 16.18.3 Abort Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 16.18.4 Handling by the DCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 16.18.5 Receive Event Oriented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 16.18.6 Receive Task Oriented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Chapter 17 LCD Controller / Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 LCD Controller/Driver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 LCD Controller/Driver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 LCD Controller/Driver Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 LCD Controller/Driver Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 LCD Display Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Common Signals and Segment Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Supplying LCD Drive Voltage VLC0, VLC1, and VLC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 17.8.1 4-time-division display example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 17.9 Cautions on Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 17.9.1 LCD timer control register (LCDTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Chapter 18 Sound Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 18.1 18.2 18.3 18.4 Sound Generator Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Sound Generator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Sound Generator Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Sound Generator Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 18.4.1 To output basic cycle signal SGOF (without amplitude) . . . . . . . . . . . . . . . . . . 335 18.4.2 To output basic cycle signal SGO (with amplitude) . . . . . . . . . . . . . . . . . . . . . 336 Chapter 19 Meter Controller / Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 19.1 19.2 19.3 19.4 Meter Controller/Driver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Meter Controller/Driver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Meter Controller/Driver Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Meter Controller/Driver Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.4.1 Basic operation of free-running up counter (SMCNT) . . . . . . . . . . . . . . . . . . . 346 19.4.2 Update of PWM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 19.4.3 Operation of 1-bit addition circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 19.4.4 PWM output operation (output with 1 clock shifted) . . . . . . . . . . . . . . . . . . . . . 349 Chapter 20 Interrupt Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 20.1 20.2 20.3 20.4 Interrupt Function Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Interrupt Sources and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Interrupt Function Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Interrupt Servicing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 20.4.1 Non-maskable interrupt request acknowledge operation . . . . . . . . . . . . . . . . . 361 20.4.2 Maskable interrupt request acknowledge operation . . . . . . . . . . . . . . . . . . . . . 363 20.4.3 Software interrupt request acknowledge operation . . . . . . . . . . . . . . . . . . . . . 366 20.4.4 Multiple interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 20.4.5 Interrupt request reserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 User's Manual U16504EE1V1UD00 13 Chapter 21 Standby Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.1 Standby Function and Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.1.1 Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.1.2 Standby function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 21.2 Standby Function Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.2.1 HALT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.2.2 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Chapter 22 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 22.1 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Chapter 23 PD78F0828A and Memory Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Memory Size Switching Register (IMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Internal Expansion RAM Size Switching Register . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Self-Programming and Oscillation Control Register . . . . . . . . . . . . . . . . . . . . . . . . 390 Flash memory programming with flash programmer. . . . . . . . . . . . . . . . . . . . . . . . 391 23.4.1 Selection of transmission method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 23.4.2 Initialization of the programming mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 23.4.3 Flash memory programming function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 23.4.4 Flash programmer connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 23.4.5 Flash programming precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 23.5 Flash Self-Programming Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 23.5.1 Flash Self-Programming Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . 395 23.1 23.2 23.3 23.4 Chapter 24 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Legends Used in Operation List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 24.1.1 Operand identifiers and description methods . . . . . . . . . . . . . . . . . . . . . . . . . . 397 24.1.2 Description of "operation" column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 24.2 Operation List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 24.3 Instructions Listed by Addressing Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 24.1 Chapter 25 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 25.1 25.2 25.3 25.4 25.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . 417 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 25.5.1 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 25.5.2 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 25.5.3 Sound Generator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 25.5.4 Meter Controller / Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 25.5.5 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 25.5.6 Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics 447 25.5.7 Flash Memory Programming Characteristics: PD78F0828A(A) . . . . . . . . . . . 450 Chapter 26 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Chapter 27 Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Appendix A Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Appendix B Embedded Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 Appendix C Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Appendix D Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 14 User's Manual U16504EE1V1UD00 List of Figures Figure 1-1: Figure 1-2: Figure 1-3: Figure 2-1: Figure 2-2: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 3-9: Figure 3-10: Figure 3-11: Figure 3-12: Figure 3-13: Figure 3-14: Figure 3-15: Figure 3-16: Figure 3-17: Figure 3-18: Figure 3-19: Figure 3-20: Figure 3-21: Figure 3-22: Figure 3-23: Figure 3-24: Figure 3-25: Figure 3-26: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 4-12: Figure 4-13: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Pin Configuration ......................................................................................................... 27 78K/0 Series Expansion .............................................................................................. 29 Block Diagram ............................................................................................................. 31 Connection of IC Pins.................................................................................................. 44 Pin Input/Output Circuits (1/3) ..................................................................................... 47 Memory Map of the PD780824A ............................................................................... 51 Memory Map of the PD780826A ............................................................................... 52 Memory Map of the PD780828A ............................................................................... 53 Memory Map of the PD78F0828A ............................................................................. 54 Data Memory Addressing of PD780824A ................................................................. 58 Data Memory Addressing of PD780826A ................................................................. 59 Data Memory Addressing of PD780828A ................................................................. 60 Data Memory Addressing of PD78F0828A ............................................................... 61 Program Counter Configuration .................................................................................. 62 Program Status Word Configuration ........................................................................... 62 Stack Pointer Configuration......................................................................................... 64 Data to be Saved to Stack Memory............................................................................. 64 Data to be Reset to Stack Memory ............................................................................. 64 General Register Configuration ................................................................................... 65 Relative Addressing .................................................................................................... 70 Immediate Addressing................................................................................................. 71 Table Indirect Addressing............................................................................................ 72 Register Addressing .................................................................................................... 73 Register Addressing .................................................................................................... 75 Direct addressing ........................................................................................................ 76 Short direct addressing ............................................................................................... 77 Special-Function Register (SFR) Addressing.............................................................. 78 Register indirect addressing ........................................................................................ 79 Based addressing description example....................................................................... 80 Based indexed addressing description example ......................................................... 81 Stack addressing description example ........................................................................ 82 Port Types ................................................................................................................... 83 P00 to P03 Configurations .......................................................................................... 87 P10 to P14 Configurations .......................................................................................... 88 P20 to P27 Configurations .......................................................................................... 89 P34 to P37 Configurations .......................................................................................... 90 P40 to P47 Configurations .......................................................................................... 91 P50 to P57 Configurations .......................................................................................... 92 P60 to P65 Configurations .......................................................................................... 93 P80 to P87 Configurations .......................................................................................... 94 P90 to P97 Configurations .......................................................................................... 95 Port Mode Register Format ......................................................................................... 97 Pull-Up Resistor Option Register (PUm) Format......................................................... 98 Port Function Register (PF3, PF4, PF8 and PF9) Format........................................... 99 Block Diagram of Clock Generator ............................................................................ 103 Processor Clock Control Register Format ................................................................. 104 External Circuit of Main System Clock Oscillator ...................................................... 105 Examples of Oscillator with Bad Connection (1/3) .................................................... 106 System Clock and CPU Clock Switching................................................................... 111 Timer 2 (TM2) Block Diagram ................................................................................... 113 16-Bit Timer Mode Control Register (TMC2) Format ................................................ 116 Capture Pulse Control Register (CRC2) Format ....................................................... 117 Prescaler Mode Register (PRM2) Format ................................................................. 118 Configuration Diagram for Pulse Width Measurement by Using the Free Running Counter .......................................................................... 119 User's Manual U16504EE1V1UD00 15 Figure 6-6: Figure 6-7: Figure 6-8: Figure 6-9: Figure 6-10: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 7-8: Figure 7-9: Figure 7-10: Figure 7-11: Figure 7-12: Figure 7-13: Figure 7-14: Figure 7-15: Figure 7-16: Figure 7-17: Figure 7-18: Figure 7-19: Figure 7-20: Figure 7-21: Figure 7-22: Figure 7-23: Figure 7-24: Figure 7-25: Figure 8-1: Figure 8-2: Figure 8-3: Figure 8-4: Figure 8-5: Figure 9-1: Figure 9-2: Figure 9-3: Figure 10-1: Figure 10-2: Figure 10-3: Figure 11-1: Figure 11-2: Figure 11-3: Figure 11-4: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: Figure 12-5: Figure 12-6: Figure 12-7: Figure 12-8: Figure 12-9: Figure 12-10: Figure 12-11: 16 Timing of Pulse Width Measurement Operation by Using the Free Running Counter and One Capture Register (with Both Edges Specified).............................. 120 CR2m Capture Operation with Rising Edge Specified .............................................. 121 Timing of Pulse Width Measurement Operation by Free Running Counter (with Both Edges Specified) ...................................................................................... 122 16-Bit Timer Register Start Timing ............................................................................ 123 Capture Register Data Retention Timing................................................................... 123 8-Bit Timer/Event Counter 50 Block Diagram............................................................ 129 8-Bit Timer/Event Counter 51 Block Diagram............................................................ 130 Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Output Control Circuit ...... 130 Timer Clock Select Register 50 Format..................................................................... 132 Timer Clock Select Register 51 Format..................................................................... 133 8-Bit Timer Mode Control Register 50 Format........................................................... 134 8-Bit Timer Mode Control Register 51 Format (1/2) .................................................. 135 Port Mode Register 3 Format .................................................................................... 136 Port Mode Register 9 Format .................................................................................... 137 8-Bit Timer Mode Control Register Settings for Interval Timer Operation ................. 138 Interval Timer Operation Timings (1/3)...................................................................... 139 8-Bit Timer Mode Control Register Setting for External Event Counter Operation.... 143 External Event Counter Operation Timings (with Rising Edge Specified) ................. 143 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation ..... 144 Square-wave Output Operation Timing ..................................................................... 145 8-Bit Timer Control Register Settings for PWM Output Operation ............................ 146 PWM Output Operation Timing (Active high setting)................................................. 147 PWM Output Operation Timings (CRn0 = 00H, active high setting) ......................... 147 PWM Output Operation Timings (CRn = FFH, active high setting) ........................... 148 PWM Output Operation Timings (CRn changing, active high setting)....................... 148 8-Bit Timer Mode Control Register Settings for 16-Bit Interval Timer Operation....... 149 16-Bit Resolution Cascade Mode (with TM50 and TM51)......................................... 151 8-bit Timer Registers 50 and 51 Start Timings .......................................................... 153 External Event Counter Operation Timings ............................................................... 153 Timings after Compare Register Change during Timer Count Operation ................. 154 8-Bit Timer/Event Counter 52 Block Diagram............................................................ 156 Timer Clock Select Register 52 Format..................................................................... 157 8-Bit Timer Output Control Register Format.............................................................. 158 8-Bit Timer Mode Control Register Settings for Interval Timer Operation ................. 159 Interval Timer Operation Timings (1/3)...................................................................... 159 Block Diagram of Watch Timer.................................................................................. 163 Watch Timer Mode Control Register (WTM) Format (1/2) ........................................ 165 Operation Timing of Watch Timer/Interval Timer....................................................... 168 Watchdog Timer Block Diagram................................................................................ 171 Timer Clock Select Register 2 Format....................................................................... 172 Watchdog Timer Mode Register Format ................................................................... 173 Remote Controlled Output Application Example ....................................................... 177 Clock Output Control Circuit Block Diagram.............................................................. 178 Timer Clock Select Register 0 Format....................................................................... 179 Port Mode Register 6 Format .................................................................................... 180 A/D Converter Block Diagram ................................................................................... 181 Power-Fail Detection Function Block Diagram .......................................................... 182 A/D Converter Mode Register (ADM1) Format.......................................................... 184 Analog Input Channel Specification Register (ADS1) Format ................................... 185 Power-Fail Compare Mode Register (PFM) Format.................................................. 186 Power-fail compare threshold value register (PFT) ................................................... 186 Basic Operation of 8-Bit A/D Converter..................................................................... 187 Relation between Analog Input Voltage and A/D Conversion Result ........................ 189 A/D Conversion ......................................................................................................... 191 Example Method of Reducing Current Consumption in Standby Mode .................... 192 Analog Input Pin Handling ......................................................................................... 193 User's Manual U16504EE1V1UD00 Figure 12-12: Figure 12-13: Figure 13-1: Figure 13-2: Figure 13-3: Figure 13-4: Figure 13-5: Figure 14-1: Figure 14-2: Figure 14-3: Figure 14-4: Figure 14-5: Figure 14-6: Figure 14-7: Figure 14-8: Figure 14-9: Figure 14-10: Figure 15-1: Figure 15-2: Figure 15-3: Figure 15-4: Figure 15-5: Figure 15-6: Figure 15-7: Figure 15-8: Figure 15-9: Figure 15-10: Figure 15-11: Figure 15-12: Figure 15-13: Figure 16-1: Figure 16-2: Figure 16-3: Figure 16-4: Figure 16-5: Figure 16-6: Figure 16-7: Figure 16-8: Figure 16-9: Figure 16-10: Figure 16-11: Figure 16-12: Figure 16-13: Figure 16-14: Figure 16-15: Figure 16-16: Figure 16-17: Figure 16-18: Figure 16-19: Figure 16-20: Figure 16-21: Figure 16-22: Figure 16-23: Figure 16-24: Figure 16-25: Figure 16-26: Figure 16-27: Figure 16-28: A/D Conversion End Interrupt Request Generation Timing....................................... 194 D/A Converter Mode Register (DAM0) Format.......................................................... 195 Block Diagram of SIO30 ............................................................................................ 197 Format of Serial Operation Mode Register (CSIM30) ............................................... 199 Format of Serial Operation Mode Register (CSIM30) ............................................... 200 Format of Serial Operation Mode Register (CSIM30) ............................................... 201 Timing of Three-wire Serial I/O Mode........................................................................ 202 Block Diagram of SIO31 ............................................................................................ 206 Format of Serial Operation Mode Register (CSIM31) ............................................... 208 Format of Serial Mode Switch Register (SIOSWI)..................................................... 209 Format of Serial Operation Mode Register (CSIM31) ............................................... 210 Format of Serial Operation Mode Register (CSIM31) ............................................... 211 Format of Serial Mode Switch Register (SIOSWI)..................................................... 212 Format of Serial Operation Mode Register (CSIM31) ............................................... 213 Format of Serial Mode Switch Register (SIOSWI)..................................................... 214 Timing of Three-wire Serial I/O Mode........................................................................ 215 Timing of Two-wire Serial I/O Mode .......................................................................... 215 Block Diagram of UART ............................................................................................ 217 Format of Asynchronous Serial Interface Mode Register (ASIM0) (1/2) ................... 220 Format of Asynchronous Serial Interface Status Register (ASIS0) ........................... 222 Format of Baud Rate Generator Control Register (BRGC0) (1/2)............................. 223 Register Settings ....................................................................................................... 225 Format of Asynchronous Serial Interface Mode Register (ASIM0) (1/2) ................... 226 Format of Asynchronous Serial Interface Status Register (ASIS0) ........................... 228 Format of Baud Rate Generator Control Register (BRGC0) (1/2)............................. 229 Error Tolerance (when k = 0), including Sampling Errors.......................................... 232 Format of Transmit/Receive Data in Asynchronous Serial Interface......................... 233 Timing of Asynchronous Serial Interface Transmit Completion Interrupt .................. 235 Timing of Asynchronous Serial Interface Receive Completion Interrupt ................... 236 Receive Error Timing................................................................................................. 237 Data Frame ............................................................................................................... 241 Remote Frame .......................................................................................................... 241 Data Frame ............................................................................................................... 242 Arbitration Field/Standard Format Mode ................................................................... 242 Arbitration Field/Extended Format Mode................................................................... 243 Control Field (Standard Format Mode)...................................................................... 244 Control Field (Extended Format Mode) ..................................................................... 244 Data Field .................................................................................................................. 245 CRC Field .................................................................................................................. 245 ACK Field .................................................................................................................. 246 End of Frame............................................................................................................. 246 Interframe Space/Error Active ................................................................................... 247 Interframe Space/Error Passive ................................................................................ 247 Error Frame ............................................................................................................... 248 Overload Frame ........................................................................................................ 249 Nominal Bit Time (8 to 25 Time Quanta) ................................................................... 255 Adjusting Synchronization of the Data Bit ................................................................. 256 Bit Synchronization.................................................................................................... 257 Transmission State Shift Chart.................................................................................. 258 Reception State Shift Chart ....................................................................................... 259 Error State Shift Chart ............................................................................................... 260 Structural Block Diagram........................................................................................... 261 Connection to the CAN Bus ...................................................................................... 262 Transmit Message Definition Bits ............................................................................. 266 Transmit Identifier ..................................................................................................... 267 Transmit Data ........................................................................................................... 268 Control bits for Receive Identifier ............................................................................. 271 Receive Status Bits (1/2) .......................................................................................... 272 User's Manual U16504EE1V1UD00 17 Figure 16-29: Figure 16-30: Figure 16-31: Figure 16-32: Figure 16-33: Figure 16-34: Figure 16-35: Figure 16-36: Figure 16-37: Figure 16-38: Figure 16-39: Figure 16-40: Figure 16-41: Figure 16-42: Figure 16-43: Figure 16-44: Figure 16-45: Figure 16-46: Figure 16-47: Figure 16-48: Figure 16-49: Figure 16-50: Figure 16-51: Figure 16-52: Figure 16-53: Figure 16-54: Figure 17-1: Figure 17-2: Figure 17-3: Figure 17-4: Figure 17-5: Figure 17-6: Figure 17-7: Figure 17-8: Figure 17-9: Figure 17-10: Figure 17-11: Figure 17-12: Figure 18-1: Figure 18-2: Figure 18-3: Figure 18-4: Figure 18-5: Figure 18-6: Figure 18-7: Figure 19-1: Figure 19-2: Figure 19-3: Figure 19-4: Figure 19-5: Figure 19-6: Figure 19-7: Figure 19-8: Figure 19-9: Figure 19-10: Figure 20-1: Figure 20-2: 18 Receive Identifier ...................................................................................................... 274 Receive Data ............................................................................................................ 275 Identifier Compare with Mask .................................................................................... 277 Control Bits for Mask Identifier ................................................................................. 278 Mask Identifier .......................................................................................................... 279 CAN Control Register (1/2) ....................................................................................... 280 DCAN Support........................................................................................................... 281 Time Stamp Function ................................................................................................ 283 SOFOUT Toggle Function......................................................................................... 283 Global Time System Function ................................................................................... 283 CAN Error Status Register (1/3) ............................................................................... 284 Transmit Error Counter ............................................................................................. 287 Receive Error Counter .............................................................................................. 287 Message Count Register (MCNT) (1/2) .................................................................... 288 Bit Rate Prescaler (1/2) ............................................................................................ 290 Synchronization Control Registers 0 and 1 (1/2) ..................................................... 292 Transmit Control Register (1/2) ................................................................................ 296 Receive Message Register ....................................................................................... 298 Mask Control Register (1/2) ...................................................................................... 299 Redefinition Control Register (1/2) ........................................................................... 302 Initialization Flow Chart ............................................................................................. 309 Transmit Preparation ................................................................................................. 310 Transmit Abort ........................................................................................................... 311 Handling of Semaphore Bits by DCAN-Module......................................................... 312 Receive with Interrupt, Software Flow ....................................................................... 313 Receive, Software Polling.......................................................................................... 314 LCD Controller/Driver Block Diagram........................................................................ 316 LCD Clock Select Circuit Block Diagram................................................................... 316 LCD Display Mode Register (LCDM) Format ............................................................ 317 LCD Display Control Register (LCDC) Format .......................................................... 318 Relationship between LCD Display Data Memory Contents and Segment/Common Outputs319 Common Signal Waveform........................................................................................ 321 Common Signal and Segment Signal Voltages and Phases..................................... 321 Example of Connection of LCD Drive Power Supply (1/2) ........................................ 322 4-Time-Division LCD Display Pattern and Electrode Connections............................ 324 4-Time-Division LCD Panel Connection Example ..................................................... 325 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ........................ 326 LCD Timer Control Register (LCDTM) Format .......................................................... 327 Sound Generator Block Diagram............................................................................... 329 Concept of Each Signal ............................................................................................. 330 Sound Generator Control Register (SGCR) Format (1/2) ......................................... 331 Sound Generator Buzzer Control Register (SGBR) Format...................................... 333 Sound Generator Amplitude Register (SGAM) Format ............................................. 334 Sound Generator Output Operation Timing............................................................... 335 Sound Generator Output Operation Timing............................................................... 336 Meter Controller/Driver Block Diagram...................................................................... 337 1-bit Addition Circuit Block Diagram .......................................................................... 338 Timer Mode Control Register (MCNTC) Format........................................................ 341 Compare Control Register n (MCMPCn) Format ...................................................... 342 Port Mode Control Register (PMC) Format (1/2)....................................................... 343 Meter Controller/Driver Clock Register (SMSWI) Format.......................................... 345 Restart Timing after Count Stop (Count Start AE Count Stop AE Count Start) ........... 346 Update of PWM data ................................................................................................. 347 Timing in 1-bit Addition Circuit Operation .................................................................. 348 Timing of Output with 1 Clock Shifted ....................................................................... 349 Basic Configuration of Interrupt Function (1/2).......................................................... 353 Interrupt Request Flag Register Format .................................................................... 356 User's Manual U16504EE1V1UD00 Figure 20-3: Figure 20-4: Figure 20-5: Figure 20-6: Figure 20-7: Figure 20-8: Figure 20-9: Figure 20-10: Figure 20-11: Figure 20-12: Figure 20-13: Figure 20-14: Figure 21-1: Figure 21-2: Figure 21-3: Figure 21-4: Figure 21-5: Figure 21-6: Figure 22-1: Figure 22-2: Figure 22-3: Figure 22-4: Figure 23-1: Figure 23-2: Figure 23-3: Figure 23-4: Figure 23-5: Figure 23-6: Figure 23-7: Figure 23-8: Figure A-1: Interrupt Mask Flag Register Format......................................................................... 357 Priority Specify Flag Register Format........................................................................ 358 Formats of External Interrupt Rising Edge Enable Register and External Interrupt Falling Edge Enable Register359 Program Status Word Format ................................................................................... 360 Flowchart from Non-Maskable Interrupt Generation to Acknowledge ...................... 361 Non-Maskable Interrupt Request Acknowledge Timing ............................................ 362 Non-Maskable Interrupt Request Acknowledge Operation ....................................... 362 Interrupt Request Acknowledge Processing Algorithm ............................................. 364 Interrupt Request Acknowledge Timing (Minimum Time).......................................... 365 Interrupt Request Acknowledge Timing (Maximum Time)......................................... 365 Multiple Interrupt Example (1/2) ................................................................................ 368 Interrupt Request Hold .............................................................................................. 371 Oscillation Stabilization Time Select Register Format............................................... 374 Standby Timing ......................................................................................................... 374 HALT Mode Clear upon Interrupt Generation ........................................................... 376 HALT Mode Release by RESET Input ...................................................................... 377 STOP Mode Release by Interrupt Generation .......................................................... 379 Release by STOP Mode RESET Input...................................................................... 380 Block Diagram of Reset Function .............................................................................. 381 Timing of Reset Input by RESET Input ..................................................................... 382 Timing of Reset due to Watchdog Timer Overflow.................................................... 382 Timing of Reset Input in STOP Mode by RESET Input ............................................. 383 Memory Size Switching Register Format .................................................................. 388 Internal Expansion RAM Size Switching Register Format......................................... 389 Self-Programming and Oscillation Control Register Format...................................... 390 Transmission Method Selection Format .................................................................... 391 Connection of using the 3-Wire SIO30 Method ......................................................... 393 Connection of using the 3-Wire SIO30 Method with Handshake .............................. 393 Connection of using the UART Method ..................................................................... 394 Flash Self-Programming Mode Control Register Format .......................................... 395 Development Tool Configuration ............................................................................... 458 User's Manual U16504EE1V1UD00 19 20 User's Manual U16504EE1V1UD00 List of Tables Table 1-1: Table 1-2: Table 1-3: Table 2-1: Table 2-2: Table 2-3: Table 3-1: Table 3-2: Table 3-3: Table 3-4: Table 3-5: Table 3-6: Table 3-7: Table 3-8: Table 3-9: Table 3-10: Table 3-11: Table 3-12: Table 3-13: Table 4-1: Table 4-2: Table 5-1: Table 5-2: Table 6-1: Table 7-1: Table 7-2: Table 7-3: Table 7-4: Table 7-5: Table 7-6: Table 7-7: Table 7-8: Table 7-9: Table 7-10: Table 7-11: Table 7-12: Table 7-13: Table 8-1: Table 8-2: Table 9-1: Table 9-2: Table 9-3: Table 10-1: Table 10-2: Table 10-3: Table 10-4: Table 10-5: Table 11-1: Table 12-1: Table 13-1: Table 13-2: Table 14-1: Table 14-2: Table 14-3: The major functional differences between the subseries ............................................... 30 Overview of Functions .................................................................................................... 32 Differences between Flash and Mask ROM version ...................................................... 33 Pin Input/Output Types................................................................................................... 35 Non-Port Pins ................................................................................................................. 37 Types of Pin Input/Output Circuits.................................................................................. 45 Internal ROM Capacities ................................................................................................ 55 Vectored Interrupts ......................................................................................................... 56 Internal high-speed RAM................................................................................................ 57 Internal expansion RAM (including sharing with DCAN) ................................................ 57 Special Function Register List ........................................................................................ 67 Implied Addressing ......................................................................................................... 74 Register Addressing ....................................................................................................... 75 Direct addressing............................................................................................................ 76 Short direct addressing................................................................................................... 77 Special-Function Register (SFR) Addressing................................................................. 78 Register indirect addressing ........................................................................................... 79 Based addressing........................................................................................................... 80 Based indexed addressing ............................................................................................. 81 Pin Input/Output Types................................................................................................... 84 Port Configuration........................................................................................................... 86 Clock Generator Configuration ..................................................................................... 103 Maximum Time Required for CPU Clock Switchover ................................................... 110 Timer 2 Configuration ................................................................................................... 114 8-Bit Timer/Event Counter 50 Interval Times ............................................................... 126 8-Bit Timer/Event Counter 51 Interval Times ............................................................... 126 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges....................................... 127 8-Bit Timer/Event Counter 51 Square-Wave Output Ranges....................................... 127 16-Bit Timer/Event Counter TM50/TM51 Interval Times .............................................. 128 16-Bit Timer/Event Counter TM50/TM51 Square-Wave Output Ranges ..................... 128 8-Bit Timer/Event Counters 50 and 51 Configurations ................................................. 129 8-Bit Timer/Event Counters 50 Interval Times.............................................................. 142 8-Bit Timer/Event Counters 51 Interval Times.............................................................. 142 8-Bit Timer/Event Counters 50 Square-Wave Output Ranges ..................................... 145 8-Bit Timer/Event Counters 51 Square-Wave Output Ranges ..................................... 145 8-Bit Timer/Event Counters Interval Times (16-Bit Timer/Event Counter Mode).......... 152 8-Bit Timer/Event Counter Square-Wave Output Ranges (16-Bit Timer/Event Counter Mode).............................................................................. 152 8-Bit Timer 52 Interval Times ....................................................................................... 155 8-Bit Timer 52 Configurations....................................................................................... 155 Interval Timer Interval Time.......................................................................................... 164 Watch Timer Configuration........................................................................................... 164 Interval Timer Operation............................................................................................... 167 Watchdog Timer Inadvertent Program Overrun Detection Times ................................ 169 Interval Times ............................................................................................................... 170 Watchdog Timer Configuration..................................................................................... 171 Watchdog Timer Overrun Detection Time .................................................................... 174 Interval Timer Interval Time.......................................................................................... 175 Clock Output Control Circuit Configuration................................................................... 178 A/D Converter Configuration ........................................................................................ 182 Composition of SIO30 .................................................................................................. 198 List of SFRs (Special Function Registers).................................................................... 198 Composition of SIO31 .................................................................................................. 207 List of SFRs (Special Function Registers).................................................................... 207 Operating Modes and Start Trigger .............................................................................. 209 User's Manual U16504EE1V1UD00 21 Table 14-4: Table 14-5: Table 15-1: Table 15-2: Table 15-3: Table 15-4: Table 15-5: Table 16-1: Table 16-2: Table 16-3: Table 16-4: Table 16-5: Table 16-6: Table 16-7: Table 16-8: Table 16-9: Table 16-10: Table 16-11: Table 16-12: Table 16-13: Table 16-14: Table 16-15: Table 16-16: Table 16-17: Table 16-18: Table 16-19: Table 16-20: Table 16-21: Table 16-22: Table 16-23: Table 16-24: Table 16-25: Table 16-26: Table 16-27: Table 17-1: Table 17-2: Table 17-3: Table 17-4: Table 17-5: Table 17-6: Table 18-1: Table 18-2: Table 19-1: Table 20-1: Table 20-2: Table 20-3: Table 20-4: Table 21-1: Table 21-2: Table 21-3: Table 21-4: Table 22-1: Table 23-1: Table 23-2: Table 23-3: Table 23-4: Table 23-5: Table 23-6: 22 Operating Modes and Start Trigger .............................................................................. 212 Operating Modes and Start Trigger .............................................................................. 214 Configuration of UART ................................................................................................. 218 List of SFRs (Special Function Registers).................................................................... 219 Relation between 5-bit Counter's Source Clock and "n" Value .................................... 231 Relation between Main System Clock and Baud Rate ................................................. 232 Causes of Receive Errors............................................................................................. 237 Outline of the Function ................................................................................................. 239 Bit Number of the Identifier .......................................................................................... 243 RTR Setting ................................................................................................................. 243 Mode Setting ............................................................................................................... 243 Data Length Code Setting ........................................................................................... 244 Operation in the Error State ......................................................................................... 247 Definition of each Field ................................................................................................ 248 Definition of each Frame ............................................................................................. 249 Arbitration .................................................................................................................... 250 Bit Stuffing ................................................................................................................... 250 Error Types .................................................................................................................. 252 Output Timing of the Error Frame ................................................................................ 252 Types of Error .............................................................................................................. 253 Error Counter ............................................................................................................... 254 Segment Name and Segment Length ......................................................................... 255 CAN Configuration........................................................................................................ 262 SFR Definitions............................................................................................................. 263 SFR Bit Definitions ....................................................................................................... 263 Message and Buffer Configuration ............................................................................... 264 Transmit Message Format............................................................................................ 265 Receive Message Format............................................................................................. 270 Mask Function .............................................................................................................. 276 Possible Setup of the SOFOUT Function..................................................................... 282 Transmission / Reception Flag ..................................................................................... 282 Possible Reactions of the DCAN.................................................................................. 287 Mask Operation Buffers................................................................................................ 300 Interrupt Sources .......................................................................................................... 304 Maximum Number of Display Pixels............................................................................. 315 LCD Controller/Driver Configuration............................................................................. 315 COM Signals ................................................................................................................ 320 LCD Drive Voltage........................................................................................................ 321 LCD Drive Voltage Supply............................................................................................ 322 Selection and Non-Selection Voltages (COM0 to COM3) ............................................ 324 Sound Generator Configuration.................................................................................... 330 Maximum and Minimum Values of the Buzzer Output Frequency ............................... 332 Meter Controller/Driver Configuration........................................................................... 338 Interrupt Source List ..................................................................................................... 352 Various Flags Corresponding to Interrupt Request Sources ........................................ 355 Times from Maskable Interrupt Request Generation to Interrupt Service .................... 363 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ................. 367 HALT Mode Operating Status ...................................................................................... 375 Operation after HALT Mode Release ........................................................................... 377 STOP Mode Operating Status...................................................................................... 378 Operation after STOP Mode Release........................................................................... 380 Hardware Status after Reset ........................................................................................ 383 Differences among PD78F0828A and Mask ROM Versions...................................... 387 Values to be set after Reset for the Memory Size Switching Register ......................... 388 Examples of internal Expansion RAM Size Switching Register Settings ..................... 389 Values when the Internal Expansion RAM Size Switching Register is Reset .............. 389 Transmission Method List............................................................................................. 391 Main Functions of Flash Memory Programming........................................................... 392 User's Manual U16504EE1V1UD00 Table 24-1: Table 24-2: Table 24-3: Table 24-4: Table 24-5: Table 24-6: Operand Identifiers and Description Methods .............................................................. 397 Operation List ............................................................................................................... 399 8-bit instructions ........................................................................................................... 407 16-bit instructions ......................................................................................................... 408 Bit manipulation instructions......................................................................................... 408 Call/instructions/branch instructions ............................................................................. 409 User's Manual U16504EE1V1UD00 23 24 User's Manual U16504EE1V1UD00 Chapter 1 Outline (PD780828A Subseries) 1.1 Features * Internal memory Item Part Number PD780824A PD780826A PD780828A PD78F0828A Program Memory (ROM) 32 Kbytes 48 Kbytes 60 Kbytes 59.5 Kbytes Data Memory Internal high-speed RAM 1024 bytes 1024 bytes 1024 bytes 1024 bytes LCD Display RAM 28 bytes 28 bytes 28 bytes 28 bytes Internal Expansion RAM 480 bytes 480 bytes 2016 bytes 2016 bytes Package 80-pin plastic QFP (fine pitch) 80-pin plastic QFP (fine pitch) 80-pin plastic QFP (fine pitch) 80-pin plastic QFP (fine pitch) * * * * * * * Instruction execution time can be changed I/O ports: 59 8-bit resolution A/D converter: 5 channels Sound generator LCD-controller / driver Meter controller / driver CAN-Interface * * * * * * Serial interface 3-wire mode 2-wire/3-wire mode UART mode Timer Supply voltage : 3 channels : 1 channel : 1 channel : 1 channel : 6 channels : VDD = 4.0 to 5.5 V The CAN macro is qualified according the requirements of ISO 11898 using the test procedures defined by ISO 16845 and passed successfully the test procedures as recommended by C & S / FH Wolfenbuettel. 1.2 Application Dashboard, climate controller, security unit etc. User's Manual U16504EE1V1UD00 25 Chapter 1 Outline (PD780828A Subseries) 1.3 Ordering Information Part Number PD780824AGC(A)-xxx-8BT PD780824AGC(A1)-xxx-8BT PD780824AGC(A2)-xxx-8BT PD780826AGC(A)-xxx-8BT PD780826AGC(A1)-xxx-8BT PD780826AGC(A2)-xxx-8BT PD780828AGC(A)-xxx-8BT PD780828AGC(A1)-xxx-8BT PD780828AGC(A2)-xxx-8BT PD78F0828AGC(A)-8BT Package 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Flash Memory Remark: xxx indicates ROM code suffix. 1.4 Quality Grade Part Number PD780824AGC(A)-xxx-8BT PD780824AGC(A1)-xxx-8BT PD780824AGC(A2)-xxx-8BT PD780826AGC(A)-xxx-8BT PD780826AGC(A1)-xxx-8BT PD780826AGC(A2)-xxx-8BT PD780828AGC(A)-xxx-8BT PD780828AGC(A1)-xxx-8BT PD780828AGC(A2)-xxx-8BT PD78F0828AGC(A)-8BT Package 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) Quality Grade Special Special Special Special Special Special Special Special Special Special Remark: xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Device" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 26 User's Manual U16504EE1V1UD00 Chapter 1 Outline (PD780828A Subseries) 1.5 Pin Configuration (Top View) * 80-pin plastic QFP (14 x 14 mm) PD780824AGC(A)- xxx - 8BT, PD780824AGC(A1)- xxx - 8BT, PD780824AGC(A2)- xxx - 8BT PD780826AGC(A)- xxx - 8BT, PD780826AGC(A1)- xxx - 8BT, PD780826AGC(A2)- xxx - 8BT PD780828AGC(A)- xxx - 8BT, PD780828AGC(A1)- xxx - 8BT, PD780828AGC(A2)- xxx - 8BT PD78F0828AGC(A) - 8BT Figure 1-1: Pin Configuration P47/S0 COM3 COM2 COM1 COM0 VLCD S15/P80 S16/P97 S17/P96 S18/SI31/P95 S19/SO31/SIO31/P94 S20/SCK31/P93 S21/TPO/P92 S22/TIO51/P91 S23/TI22/P90 S24/SI30/P37 S25/SO30/P36 S26/SCK30/P35 S27/TIO50/P34 IC/Vpp X1 X2 VSS0 VDD0 CTXD CRXD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P81/S14 P82/S13 P83/S12 P84/S11 P85/S10 P86/S9 P87/S8 P40/S7 P41/S6 P42/S5 P43/S4 P44/S3 P45/S2 P46/S1 SMVSS SMVDD SM11/P20 SM12/P21 SM13/P22 SM14/P23 SM21/P24 SM22/P25 SM23/P26 SM24/P27 SM31/P50 SM32/P51 SM33/P52 SM34/P53 SM41/P54 SM42/P55 SM43/P56 SM44/P57 SMVDD SMVSS AVss ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 AVDD/AVREF VSS1 VDD1 INTP0/P00 Cautions: 1. Connect IC (internally connected) pin directly to VSS. 2. AVDD pin should be connected to VDD. 3. AVSS pin should be connected to VSS. Remark: When these devices are used in applications, that require reduction of the noise, generated from inside the microcontroller, the implementation of noise reduction measures, such as connecting the VSS0 and VSS1 to different ground lines, is recommended. User's Manual U16504EE1V1UD00 27 RxD0/P62 SGOA/PCL/P61 SGO/SGOF/P60 RESET INTP1/P01 INTP2/P02 CCLK/P03 TI21/P65 TI20/P64 TxD0/P63 Chapter 1 Pin Identifications Outline (PD780828A Subseries) P00 to P03 P10 to P14 P20 to P27 P34 to P37 P40 to P47 P50 to P57 P60 to P65 P80 to P87 P90 to P97 INTP0 to INTP2 TI50, TI51 TI20 to TI22 TO51, TO52 TPO CRXD CTXD CCLK SI30, SI31 SO30, SO31 SCK30, SCK31 SIO31 RXD0 TXD0 : : : : : : : : : : : : : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 8 Port 9 Interrupt from Peripherals Timer Input Timer Input Timer Output Timer Output CAN Receive Data CAN Transmit Data CAN Clock Serial Input Serial Output Serial Clock Serial Input/Output Receive Data Transmit Data SGO SGOA SGOF PCL SM11 to SM14 SM21 to SM24 SM31 to SM34 SM41 to SM44 SMVDD SMVSS S0 to S27 COM0 to COM3 X1, X2 RESET ANI0 to ANI4 AVSS AVDD/AVREF : : : : : : : : : : : : : : : : : : Sound Generator Output Sound Generator Amplitude Sound Generator Frequency Programmable Clock Output Meter Controller/Driver Meter Controller/Driver Meter Controller/Driver Meter Controller/Driver Meter Controller/Driver Meter Controller/Driver Segment Output Common Output Crystal (Main System Clock) Reset Analog Input Analog Ground Analog Reference Voltage and ADC Power Supply Power Supply Programming Power Supply Ground Internally Connected VDD0, VDD1 VPP VSS0, VSS1 IC : : : : : 28 User's Manual U16504EE1V1UD00 Chapter 1 Outline (PD780828A Subseries) 1.6 78K/0 Series Expansion The following shows the products organized according to usage. The names in the parallelograms are subseries. Figure 1-2: 78K/0 Series Expansion Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 42/44-pin PD78075B PD78078 PD78070A PD780058 PD780065 PD780078 PD780034A PD780024A PD78083 Inverter control EMI-noise reduced version of the PD78078 PD78078Y PD78070AY PD780018AY PD780058Y PD780078Y PD780034AY PD780024AY PD78054 with timer and enhanced external interface ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited function PD78054 with enhanced serial I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780024A with enhanced A/D converter PD78018F with enhanced serial I/O On-chip UART, capable of operating at low voltage (1.8 V) 64-pin PD780988 VFD drive On-chip inverter control circuit and UART. EMI-noise reduced. 100-pin 78K/0 Series 80-pin 80-pin 80-pin PD780208 PD780232 PD78044H PD78044F LCD drive PD78044F with enhanced I/O and VFD C/D. Display output total: 53 For panel control. On-chip VFD C/D. Display output total: 53 PD78044F with N-ch open-drain I/O. Display output total: 34 Basic subseries for driving VFD. Display output total: 34 120-pin 120-pin 120-pin 100-pin 100-pin 100-pin PD780338 PD780328 PD780318 PD780308 PD78064B PD78064 PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. PD780308 with enhanced display function and timer. Segment signal output: 24 pins max. PD780308Y PD78064Y PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, on-chip UART Bus interface supported 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 100-pin 80-pin 80-pin PD780948 PD78098B PD780702Y PD780703Y PD780833Y PD780816 Meter control On-chip CAN controller PD78054 with IEBusTM controller On-chip IEBus controller On-chip CAN controller On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller PD780958 PD780852 PD780828A Remark: VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. User's Manual U16504EE1V1UD00 29 Chapter 1 Outline (PD780828A Subseries) The major functional differences between the subseries are shown below. Table 1-1: Function Subseries Name The major functional differences between the subseries Timer 8-bit 16-bit WT WDT 8-bit 10-bit 8-bit A/D A/D D/A Serial Interface I/O VDD External MIN Expansion value 1.8 V 2.7 V 1.8 V O 2.7 V ROM Capacity (Bytes) PD78075B 32K to 40K 88 PD78078 48K to 60K 4 ch 2 ch 1 ch 1 ch Control PD780065 40K to 48K PD780078 48K to 60K 2 ch PD780034A 8K to 32K PD780024A 8 ch PD78083 Inverter control 8K to 16K Note 1 ch 1 ch 1 ch 1 ch PD78044H 32K to 48K 2 ch PD78044F 16K to 40K PD780338 PD780328 48K to 60K 3 ch PD780318 LCD drive PD780308 48K to 60K PD78064B 32K PD78064 16K to 32K 2 ch 8 ch 1 ch 2 ch 2 ch 1 ch 1 ch 1 ch 12 ch 2 ch 3 ch (UART: 1 ch) 69 2 ch (UART: 1 ch) 46 2 ch (UART: 1 ch) 69 56 1 ch 1 ch 1 ch 5 ch 3 ch (UART: 1 ch) 59 4.0 V 2.7 V 4.0 2.2 V 79 4.0 V O 2 ch 1 ch 8 ch 2 ch (UART: 1 ch) PD780948 60 K Bus PD78098B 40K to 60K 2 ch interface supported PD780816 32K to 60K Meter control PD780958 48K to 60K 4 ch 1 ch 1 ch 3 ch (time-division UART: 1 ch) 57 2.0 V 2 ch 10 ch 1 ch 8 ch 2 ch 54 1 ch 2 ch (UART: 1 ch) 62 70 1.8 V 1 ch 8 ch 2 ch PD780232 16K to 24K 3 ch VFD drive 4 ch 1 ch 68 2.7 V 40 4.5 V 8 ch 1 ch (UART: 1 ch) 33 2 ch (UART: 2 ch) 47 74 4.0 V 2.7 V O 1 ch 2 ch 8 ch 3 ch (UART: 1 ch) 51 1.8 V 1 ch 8 ch 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 61 68 PD78070A PD780058 24K to 60K 4 ch (UART: 1 ch) 60 3 ch (UART: 2 ch) 52 PD780988 16K to 60K 3 ch PD780208 32K to 60K 2 ch Dashboard PD780852 32K to 40K 3 ch control PD780828A 32K to 60K Note: 16-bit timer: 2 channels 10-bit timer: 1 channel 30 User's Manual U16504EE1V1UD00 Chapter 1 Outline (PD780828A Subseries) 1.7 Block Diagram Figure 1-3: VDD0 VDD1 VSS0 VSS1 Block Diagram IC/VPP TPO21/S21/P92 TI20/P64 TI21/P65 TI22/S23/P90 TIO50/S27/P34 TIO51/S22/P91 16-bit Timer TM2 3 x Capture with Filter 8-bit Timer TM50 8-bit Timer TM51 8-bit Timer TM52 Watch Timer Port 0 Port 1 Port 2 P00 - P03 P10 - P14 P20 - P27 P34 - P37 P40 - P47 P50 - P57 P60 - P65 P80 - P87 P90 - P97 S0/P47 - S7/P40 S8/P87 - S15/P80 System Control 4.0 V - 5.5 V X1 X2 RESET Port 3 Port 4 Port 5 Watchdog Timer SCK30/S26/P35 SO30/S25/P36 SI30/S24/P37 SCK31/S20/P93 SO31/SIO31/S19/P94 SI31/S18/P95 RxD0/P62 TxD0/P63 ANI0/P10 -ANI4/P14 AVDD/AVREF AVSS Serial Interface SIO30 3-wire mode 78K/0 CPU Core Port 6 ROM RAM Port 8 Port 9 Serial Interface SIO31 3-wire/2-wire mode UART0 Interface A/D Converter Power Fail Detector LCD Controller driver CRxD CTxD CCLK S16/P97 - S23/P90 S23/P37 - S27/P34 INTP0/P00 -INTP2/P02 Interrupt Control Standby Control DCAN Interface RAM COM0 - COM3 VLCD SM11/P20 - SM14/P23 PCL/SGOA/P61 SGO/SGOF/P60 Clock Output Control Sound Generator Output SM21/P24 - SM24/P27 Meter Controller/ Driver SM31/P50 - SM34/P53 SM41/P54 - SM44/P57 SMVDD SMVDD SMVSS SMVSS Remark: The internal ROM and RAM capacity depends on the product. User's Manual U16504EE1V1UD00 31 Chapter 1 Outline (PD780828A Subseries) 1.8 Overview of Functions Table 1-2: Item ROM Hi-speed RAM Expansion RAM LCD Display RAM Memory space General register Main system clock 8 bits - 32 registers PD78F0828A 59.5 Kbytes Flash EE Overview of Functions PD780828A 60 Kbytes Mask ROM PD780826A 48 Kbytes Mask ROM 1024 bytes PD780824A 32 Kbytes Mask ROM 2016 bytes 28 bytes 64 Kbytes (8 bit x 8 x 4 bank) 480 bytes 0.25 s/0.5 s/1 s/2 s/4 s (at 8 MHz) * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD adjustment, etc. Instruction set I/O port 59 in total Input ports: 5 Output ports: 16 I/O ports: 38 8 bit x 5 channels 3-wire mode: 1 channel 2-wire/3-wire mode: 1 channel UART: 1 channel 16 bit timer / event counter: 1 channel 8 bit timer / event counter: 2 channels 8 bit interval timer: 1 channel Watch timer: 1 channel Watchdog timer: 1 channel 3 outputs (8-bit PWM output x 2) 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 KHz, 250 KHz, 125 KHz, 62.5 KHz @fX = 8 MHz 1 output Segment output: 28, Common output: 4 1 channel Non-maskable interrupt: 1 (internal) Maskable interrupt: 20 (internal) External interrupt: 3 Software interrupt: 1 VDD = 4.0 V to 5.5 V 80-QFP (14 x 14) A/D converter Serial I/F Timer Timer output Clock output Sound Generator LCD CAN Vectored interrupt Operating voltage range Package 32 User's Manual U16504EE1V1UD00 Chapter 1 Outline (PD780828A Subseries) 1.9 Differences between Flash and Mask ROM version The differences between the two versions are shown in the table below. Differences of the electrical specification are given in the data sheet. Table 1-3: Differences between Flash and Mask ROM version Flash Version Mask ROM Version Mask ROM None (IC pin) 480 bytes PD780824A ROM VPP Pin Internal Expansion RAM Flash EEPROM Yes 2016 bytes 480 bytes PD780826A 2016 bytes PD780828A User's Manual U16504EE1V1UD00 33 [MEMO] 34 User's Manual U16504EE1V1UD00 Chapter 2 2.1 Pin Function List Pin Function (PD780828A Subseries) Normal Operating Mode Pins / Pin Input/Output Types Table 2-1: Pin Input/Output Types (1/2) Input/Output Pin Name P00 Input/Output P01 P02 P03 Input P10-P14 P20 P21 P22 Input/Output P23 P24 P25 P26 P27 P34 P35 Input/Output P36 P37 Port 3 4 bit input / output port input / output mode can be specified bit-wise If used as an input port, a pull-up resistor can be connected by software bit-wise This port can be used as a segment signal output port or an I/O port in 1 bit unit by setting port function Port 4 8 bit input / output port input / output mode can be specified bit-wise If used as an input port, a pull-up resistor can be connected by software bit-wise This port can be used as a segment output port or an I/O port, in 8 bit unit by setting port function Port 2 8 bit output port Function Port 0 4 bit input / output port input / output mode can be specified bit-wise If used as an input port, a pull-up resistor can be connected by software bit-wise Port 1 5 bit input port Alternate Function INTP0 INTP1 INTP2 CCLK ANI0-ANI4 SM11 SM12 SM13 SM14 SM21 SM22 SM23 SM24 TI50/TO50/S27 SCK30/S26 SO30/S25 SI30/S24 After Reset Input Input Input Input Input Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Input Input Input Input Input/Output P40-P47 S0-S7 Input P50 P51 P52 Input/Output P53 P54 P55 P56 P57 Port 5 8 bit output port SM31 SM32 SM33 SM34 SM41 SM42 SM43 SM44 Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z User's Manual U16504EE1V1UD00 35 Chapter 2 Pin Function (PD780828A Subseries) Table 2-1: Pin Input/Output Types (2/2) Input/Output Pin Name P60 P61 Input/Output P62 P63 P64 P65 Port 7 8 bit input / output port input / output mode can be specified bit-wise If used as an input port, a pull-up resistor can be connected by software bit-wise This port can be used as a segment signal output port or an I/O port in 1 bit units by setting port function Port 6 6 bit input / output port input / output mode can be specified bit-wise If used as an input port, a pull-up resistor can be connected by software bit-wise Function Alternate Function SGOF/SGO SGOA/PCL RXD0 TXD0 TI20 TI21 After Reset Input Input Input Input Input Input Input/Output P80-P87 S15-S8 Input P90 P91 P92 Input/Output P93 P94 P95 P96 P97 Port 9 8 bit input / output port input / output mode can be specified bit-wise If used as an input port, a pull-up resistor can be connected by software bit-wise This port can be used as a segment signal output port or an I/O port in 1 bit units by setting port function TI22/S23 TI51/TO51/S22 TPO/S21 SCK31/S20 SO31/SIO31/S19 SI31/S18 S17 S16 Input Input Input Input Input Input Input Input 36 User's Manual U16504EE1V1UD00 Chapter 2 Pin Function (PD780828A Subseries) 2.2 Non-Port Pins Table 2-2: Pin Name INTP0 INTP1 INTP2 SI30 SI31 SO30 SO31 SCK30 SCK31 SIO31 RXD0 TXD0 CRXD CTXD TI20 TI21 TI22 TI50 TI51 TP0 TO50 TO51 PCL S0-S7 S8-S15 S16-S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 COM0-COM3 Output Output Output Output Input Input Output Output Input Input/Output Non-Port Pins (1/2) Function After Reset Alternate Function Pin P00 External interrupts with specifiable valid edges (risInput ing edge, falling edge, both rising and falling edges) Serial interface serial data input Serial interface serial data input Serial interface serial data output Serial interface serial data output Input Input Input Input Input Input Input Input Input Input Output P01 P02 P37/S24 P95/S18 P36/S25 P94/SIO31/S19 P35/S26 P93/S20 P94/SO31/S19 P62 P63 P64 P65 P90/S23 P34/TO50/S27 P91/TO51/S22 P92/S21 Input, Output Serial interface serial clock input / output Input, Output Serial interface serial clock input / output Input, Output Serial interface serial data input / output Input Output Input Output Input Input Input Input Input Asynchronous serial interface data input Asynchronous serial interface data output CAN serial data input CAN serial data output Capture trigger input Capture trigger input Capture trigger input External count clock input to 8-bit timer (TM50) External count clock input to 8-bit timer (TM51) 16-bit timer output 8-bit timer output (also used for PWM output) 8-bit timer output (also used for PWM output) Clock output (for main system clock trimming) Input P34/TI50/S27 P91/TI51/S22 Input P61/SGOA P40-P47 P80-P87 P97-P96 P95/SI31 P94/SO31/SIO31 P93/SCK31 Segment signal output of LCD controller / driver Input P92/TPO P91/TO51/TI51 P90/TI22 P37/SI30 P36/SO30 P35/SCK30 P34/TO50/TI50 Common signal output of LCD controller /driver Output - User's Manual U16504EE1V1UD00 37 Chapter 2 Pin Function (PD780828A Subseries) Table 2-2: Pin Name VLCD SGO SGOA SGOF Input/Output Output Output Output LCD drive voltage Sound generator output Sound generator amplitude output Sound generator frequency output AD converter analog input Non-Port Pins (2/2) Function Input Input Input Input After Reset P60/SGOF P61/PCL P60/SGO P10-P14 P20-P23 Alternate Function Pin ANI0 to ANI4 Input AVDD /AVREF AVSS SM11-SM14 SM21-SM24 SM31-SM34 SM41-SM44 SMVDD SMVSS RESET X1 X2 VDD0,VDD1 VSS0,VSS1 VPP IC Input Output - AD converter reference voltage input. Power supply of the AD converter. AD converter ground potential. Connect to VSS - Meter control output Hi-z P24-P27 P50-P53 P54-P57 Meter C/D power supply Meter C/D ground System reset input Crystal connection for main system clock Crystal connection for main system clock Positive power supply Ground potential High voltage supply for flash programming (only flash version) Internal connection. Connect directly to VSS (only Mask ROM version) - IC VPP 38 User's Manual U16504EE1V1UD00 Chapter 2 Pin Function (PD780828A Subseries) 2.3 Description of Pin Functions 2.3.1 P00 to P03 (Port 0) This is an 4-bit input/output port. Besides serving as input/output port the external interrupt input is implemented. (1) Port mode P00 to P03 function as input/output ports. P00 to P03 can be specified for input or output bit-wise with a port mode register. When they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register. (2) Control mode In this mode this port operates as external interrupt input. (a) INTP0 to INTP2 INTP0 to INTP2 are external input pins which can specify valid edges (rising, falling or rising and falling) of this external interrupt pins. (b) CCLK CCLK is the input pin for an external CAN clock. 2.3.2 P10 to P14 (Port 1) These pins constitute a 5-bit input only port. In addition, they are also used to input A/D converter analog signals. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P10 to P14 function as a 5-bit input only port. (2) Control mode In this mode, P10 to P14 function as A/D converter analog input pins (ANI0 to ANI4). 2.3.3 P20 to P27 (Port 2) These pins constitute an 8-bit output only port. In addition they are also used as PWM output pins to control meters. (1) Port mode In this mode, P20 to P27 function as an 8-bit output only port. (2) Control mode In this mode, P20 to P27 function as PWM output pins (SM11 to SM14 and SM21 to SM24) for meter control. User's Manual U16504EE1V1UD00 39 Chapter 2 Pin Function (PD780828A Subseries) 2.3.4 P34 to P37 (Port 3) These are 4-bit input/output ports. Besides serving as input/output ports, they function as data input/ output to/from and clock input/out of the serial interface. Additionally they function as timer input/output and segment signal output of the LCD controller/driver. The port mode and the port function can be specified bit-wise. (1) Port mode These ports function as 4-bit input/output ports. They can be specified bit-wise as input or output ports with the port mode register 3. (2) Control mode These ports function as timer input/output, as serial interface data input/output, serial clock input/output and as LCD segment output. (a) SI30, SO30 Serial interface serial data input/output pins. (b) SCK30 Serial interface serial clock input/output pin. (c) TI50 Pin for external count clock input to 8-bit timer/event counter. (d) TO50 Pin for output of the 8-bit timer/event counter. (e) S24 to S27 Pins for segment output signals of the LCD controller/driver. Caution: When this port is used as a serial interface, the I/O function and output latches must be set according to the function the user requires. 2.3.5 P40 to P47 (Port 4) This is an 8-bit input/output port. Besides serving as input/output port, they function as segment signal output pins of the LCD controller/driver. The following operating modes can be specified bit-wise or byte-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 4. (2) Control mode These port function as segment output signal pins (S0 to S7) of the LCD controller/driver and can specified byte-wise. 40 User's Manual U16504EE1V1UD00 Chapter 2 Pin Function (PD780828A Subseries) 2.3.6 P50 to P57 (Port 5) These pins constitute an 8-bit output only port. In addition they also function as PWM output pins to control meters. (1) Port mode In this mode, P50 to P57 function as an 8-bit output only port. (2) Control mode In this mode, P50 to P57 function as PWM output pins (SM31 to SM34 and SM41 to SM44) for meter control. 2.3.7 P60 to P65 (Port 6) These are 6-bit input/output ports. Beside serving as input/output ports, they function as timer input, clock output, sound generator output and as input/output of the asynchronous serial interface. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 5-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 3. (2) Control mode These ports function as timer input, clock output, as input/output of the asynchronous serial interface and sound generator output. (a) TI20, TI21 Pins for external capture trigger input to the 16-bit timer capture registers of TM2. (b) PCL Clock output pin. (c) SGO, SGOA and SGOF Pins for separate or composed signal output of the sound generator. (d) (e) RXD0, TXD0 Asynchronous serial interface data input/output pins. Caution: When this port is used as a serial interface, the I/O function and output latches must be set according to the function the user requires. User's Manual U16504EE1V1UD00 41 Chapter 2 Pin Function (PD780828A Subseries) 2.3.8 P80 to P87 (Port 8) These are 8-bit input/output ports. Besides serving as input/output ports, they function as segment signal output pins of the LCD controller/driver. The following operating modes can be specified bit-wise or byte-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 8. (2) Control mode These ports function as segment output signal pins (S8 to S15) of the LCD controller/driver. 2.3.9 P90 to P97 (Port 9) These are 8-bit input/output ports. Besides serving as input/output ports, they function as segment signal output pins of the LCD controller/driver, timer input/output and as input/output of the serial interface. The following operating modes can be specified bit-wise or byte-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 9. (2) Control mode These ports function as timer input/output, timer capture input, as timer output and as LCD segment output. (a) TI22 Pin for external capture trigger input to the 16-bit timer capture register of TM2. (b) TPO Pin for output of the 16-bit timer (TM2). (c) TI51 Pin for external count clock input to 8-bit timer/event counter. (d) TO51 Pin for output of the 8-bit timer/event counter. (e) S16 to S23 Pins for segment output signals of the LCD controller/driver. (f) SCK31 Serial interface serial clock input/output pin. (g) SI31, SO31, SIO31 Serial interface serial data input/output pins. 42 User's Manual U16504EE1V1UD00 Chapter 2 Pin Function (PD780828A Subseries) 2.3.10 CTXD This pin functions as CAN-controller transmit output. 2.3.11 CRXD This pin functions as CAN-controller receive input. 2.3.12 CCLK This pin functions as external CAN-controller clock input. 2.3.13 COM0 to COM3 These are LCD controller/driver common signal output pins. They output common signals under the following condition: - 4-time-division is performed in 1/3 bias mode. 2.3.14 VLCD This pin supplies a voltage to drive an LCD. 2.3.15 AVDD / AVREF A/D converter reference voltage input pin and the power supply for the A/D-converter. When A/D converter is not used, connect this pin to VDD. 2.3.16 AVSS This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin even when A/D converter is not used. 2.3.17 RESET This is a low-level active system reset input pin. 2.3.18 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1. 2.3.19 SMVDD This pin supplies a positive power to the meter controller/driver. 2.3.20 SMVSS This is the ground pin of the meter controller/driver. User's Manual U16504EE1V1UD00 43 Chapter 2 Pin Function (PD780828A Subseries) 2.3.21 VDD0, VDD1 VDD0 is the positive power supply pin for ports. VDD1 is the positive power supply pin for blocks other than ports. 2.3.22 VSS0, VSS1 VSS0 is the ground pin for ports. VSS1 is the ground pin for blocks other than ports. 2.3.23 VPP (PD78F0828A only) High-voltage apply pin for FLASH programming mode setting. Connect this pin directly to VSS in normal operating mode. 2.3.24 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD78F0828A at delivery. Connect it directly to the VSS with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally. Figure 2-1: Connection of IC Pins Vss IC As short as possible Caution: Connect IC pins to VSS pins directly. 44 User's Manual U16504EE1V1UD00 Chapter 2 Pin Function (PD780828A Subseries) 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in the following table. For the input/output circuit configuration of each type, see tTable 2-3, "Types of Pin Input/Output Circuits," on page 45. Table 2-3: Pin Name P00/INTP0 P01/INT01 P02/INT02 P03/CCLK P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P20/SM11 P21/SM12 P22/SM13 P23/SM14 P24/SM21 P25/SM22 P26/SM23 P27/SM24 P34/TI50/TO50/S27 P35/SCK30/S26 P36/SO30/S25 P37/SI30/S24 P40/S7 P41/S6 P42/S5 P43/S4 P44/S3 P45/S2 P46/S1 P47/S0 17-A 17-B 17-A 17-B 4 9 8-A Input/Output Circuit Type Types of Pin Input/Output Circuits (1/2) I/O Recommended Connection for Unused Pins I/O Input: Connect to VDD or VSS via a resistor individually. Output: Leave open. I Connect to VDD or VSS directly O Leave open. I/O Input: Connect to VDD or VSS via a resistor individually. Output: Leave open. I/O Input: Connect to VDD or VSS via a resistor individually. Output: Leave open. User's Manual U16504EE1V1UD00 45 Chapter 2 Pin Function (PD780828A Subseries) Table 2-3: Pin Name P50/SM31 P51/SM32 P52/SM33 P53/SM34 P54/SM41 P55/SM42 P56/SM43 P57/SM44 P60/SGOF/SGO P61/RCL/SGOA P62/RXD0 P63/TXD0 P64/TI20 P65/TI21 P80/S15 P81/S14 P82/S13 P83/S12 P84/S11 P85/S10 P86/S9 P87/S8 P90/TI22/S23 P91/TI51/TO50/S22 P92/TPO/S21 P93/SCK31/S20 P94/SO31/SIO31/S19 P95/SI31/S18 P96/S17 P97/S16 COM0-COM3 VLCD CRXD CTXD RESET AVDD / AVREF AVSS IC VPP 18 1 2 1 O I O I Leave open Connect to VSS Connect to VDD Leave open. Connect to VDD Connect to VSS Connect directly to VSS 17-B 17-B 17-B 17-A I/O Input: Connect to VDD or VSS via a resistor individually. Output: Leave open. 17-B I/O Input: Connect to VDD or VSS via a resistor individually. Output: Leave open. 5 5 8 5 8 8 I/O Input: Connect to VDD or VSS via a resistor individually. Output: Leave open. 4 O Leave open. Input/Output Circuit Type Types of Pin Input/Output Circuits (2/2) I/O Recommended Connection for Unused Pins 46 User's Manual U16504EE1V1UD00 Chapter 2 Pin Function (PD780828A Subseries) Figure 2-2: Pin Input/Output Circuits (1/3) Type 1 Type 5 V DD Data P-ch IN/OUT IN Output disable N-ch Input disable Type 2 Type 8 VDD VDD P-ch Data N-ch OUT Output disable N-ch Data P-ch IN/OUT Type 4 Type 8-A VDD VDD Data P-ch OUT Output disable N-ch Pullup enable V DD Data P-ch P-ch IN/OUT Output disable N-ch User's Manual U16504EE1V1UD00 47 Chapter 2 Pin Function (PD780828A Subseries) Figure 2-2: Pin Input/Output Circuits (2/3) Type 9 Type 17 VLC0 P-ch P-ch Comparator + N-ch VREF (Threshold Voltage) IN SEG Data P-ch Input enable VLC2 N-ch N-ch VLC1 N-ch P-ch OUT Type 17-A VDD Type 17-B VDD Pullup enable VDD Data P-ch P-ch Pullup enable V DD Data IN/OUT P-ch P-ch IN/OUT Output disable N-ch Output disable Input enable VLC0 P-ch VLC1 N-ch SEG Data P-ch VLC2 N-ch N-ch P-ch N-ch VLC0 P-ch VLC1 N-ch SEG Data P-ch VLC2 N-ch N-ch P-ch 48 User's Manual U16504EE1V1UD00 Chapter 2 Pin Function (PD780828A Subseries) Figure 2-2: Pin Input/Output Circuits (3/3) Type 18 P-ch VLC0 VLC1 OUT COM VLC2 N-ch User's Manual U16504EE1V1UD00 49 [MEMO] 50 User's Manual U16504EE1V1UD00 Chapter 3 3.1 Memory Space CPU Architecture The memory map of the PD780824A is shown in Figure 3-1. Figure 3-1: FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FB00H FAFFH FA80H FA7FH FA64H FA63H Special Function Register (SFR) 256 x 8 bits Memory Map of the PD780824A General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Not usable LCD Display RAM 28 x 4 bits 7FFFH Not usable 1000H 0FFFH F7E0H F7DFH CALLF Entry Area Expansion RAM 480 Bytes (shared with DCAN) 0800H 07FFH Program Area F600H F5FFH Program Area 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area 0000H Not usable 8000H 7FFFH Internal ROM 32 Kbytes 0000H Note: In the expansion RAM between F600H and F7DFH it is not possible to do code execution. User's Manual U16504EE1V1UD00 51 Chapter 3 CPU Architecture The memory map of the PD780826A is shown in Figure 3-2. Figure 3-2: FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FB00H FAFFH FA80H FA7FH FA64H FA63H Special Function Register (SFR) 256 x 8 bits Memory Map of the PD780826A General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Not usable LCD Display RAM 28 x 4 bits BFFFH Not usable 1000H 0FFFH F7E0H F7DFH CALLF Entry Area Expansion RAM 480 Bytes (shared with DCAN) 0800H 07FFH Program Area F600H F5FFH Program Area 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area 0000H Not usable C000H BFFFH Internal ROM 48 Kbytes 0000H Note: In the expansion RAM between F600H and F7DFH it is not possible to do code execution. 52 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture The memory map of the PD780828A is shown in Figure 3-3. Figure 3-3: FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FB00H FAFFH FA80H FA7FH FA64H FA63H Special Function Register (SFR) 256 x 8 bits Memory Map of the PD780828A General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Not usable LCD Display RAM 28 x 4 bits Not usable EFFFH Program Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH F7E0H F7DFH Expansion RAM 480 Bytes (shared with DCAN) F600H F5FFH F400H F3FFH F000H EFFFH Expansion RAM 512 Bytes Expansion RAM 1024 Bytes Program Area 0080H 007FH CALLT Table Area 0040H 003FH Internal ROM 60 Kbytes 0000H 0000H Vector Table Area Notes: 1. In the expansion RAM between F000H and F3FFH it is possible to do code execution. 2. In the expansion RAM between F400H and F7DFH it is not possible to do code execution. User's Manual U16504EE1V1UD00 53 Chapter 3 CPU Architecture The memory map of the PD78F0828A is shown in Figure 3-4. Figure 3-4: FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FB00H FAFFH FA80H FA7FH FA64H FA63H Memory Map of the PD78F0828A Special Function Register (SFR) 256 x 8 bits General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Not usable LCD Display RAM 28 x 4 bits Not usable F7E0H F7DFH EDFFH Program Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH F600H F5FFH F000H EFFFH EE00H EDFFH Expansion RAM 480 Bytes (shared with DCAN) Expansion RAM 1536 Bytes Program Area 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area 0000H Not usable Internal ROM 59.5 Kbytes 0000H Notes: 1. In the expansion RAM between F000H and F5FFH it is possible to do code execution. 2. In the expansion RAM between F600H and F7DFH it is not possible to do code execution. 54 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This is generally accessed by the program counter (PC). The PD780828A Subseries have various size of internal ROMs or Flash EPROM as shown below. Table 3-1: Part Number PD780824A PD780826A PD780828A PD78F0828A Internal ROM Capacities Internal ROM Type Mask ROM Mask ROM Mask ROM Flash EEPROM Capacity 32768 x 8-bits 49152 x 8-bits 61440 x 8-bits 60928 x 8-bits The internal program memory is divided into three areas: vector table area, CALLT instruction table area, and CALLF instruction table area. These areas are described on the next page. User's Manual U16504EE1V1UD00 55 Chapter 3 CPU Architecture (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses. Table 3-2: Vectored Interrupts Interrupt Request INWDT INTAD INTOVF INTTM20 INTTM21 INTTM22 INTP0 INTP1 INTP2 INTCE INTCR INTCT0 INTCT1 INTCSI30 INTSER0 INTSR0 INTST0 INTTM50 INTTM51 INTTM52 INTWTI INTWT INTCSI31 BRK Vector Table Address 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002EH 0030H 0032H 003EH (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 56 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture 3.1.2 Internal data memory space The PD780828A Subseries units incorporate the following RAMs. (1) Internal high-speed RAM Table 3-3: Device PD780824A PD780826A PD780828A PD78F0828A Internal high-speed RAM Internal High Speed RAM 1024 x 8 bits (FB00H to FEFFH) 1024 x 8 bits (FB00H to FEFFH) 1024 x 8 bits (FB00H to FEFFH) 1024 x 8 bits (FB00H to FEFFH) The 32-byte area FEE0H to FEFF is allocated with four general purpose register banks composed of eight 8-bit registers. The internal high-speed RAM has to be used as stack memory. (2) LCD-Display RAM Buffer RAM is allocated to the 28 x 4 bits area from FA64H to FA7FH. LCD-Display RAM can also be used as normal RAM. (3) Internal expansion RAM (including sharing with DCAN) Table 3-4: Internal expansion RAM (including sharing with DCAN) Device Internal Expansion RAM 480 x 8 bits (F600H to F7DFH) 480 x 8 bits (F600H to F7DFH) 2016 x 8 bits (F000H to F7DFH) 2016 x 8 bits (F000H to F7DFH) PD780824A PD780826A PD780828A PD78F0828A 3.1.3 Special function register (SFR) area An on-chip peripheral hardware special function register (SFR) is allocated in the area FF00H to FFFFH. (Refer to Table 3-5, "Special Function Register List," on page 67). Caution: Do not access addresses where the SFR is not assigned. User's Manual U16504EE1V1UD00 57 Chapter 3 CPU Architecture 3.1.4 Data memory addressing The PD780828A Subseries is provided with a verity of addressing modes which take account of memory manipulability, etc. Special addressing methods are possible to meet the functions of the special function registers (SFRs) and general registers. The data memory space is the entire 64K-byte space (0000H to FFFFH). Figures 3-5 to 3-8 show the data memory addressing modes. For details of addressing, refer to 3.4 "Operand Address Addressing" on page 74. Figure 3-5: FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FB00H FAFFH FA80H FA7FH FA64H FA63H Data Memory Addressing of PD780824A Special Function Register (SFR) 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Register Addressing Short Direct Addressing Not usable LCD Display RAM 28 x 4 bits Direct Addressing Register Indirect Addressing Based Addressing Not usable Based Indexed Addressing F7E0H F7DFH Expansion RAM 480 x 8 bits (shared with DCAN) Not usable F600H F5FFH 8000H 7FFFH Internal Mask ROM 32768 x 8 bits 0000H Note: In the expansion RAM between F600H and F7DFH it is not possible to do code execution. 58 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture Figure 3-6: FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FB00H FAFFH FA80H FA7FH FA64H FA63H Not usable LCD Display RAM 28 x 4 bits Direct Addressing Register Indirect Addressing Based Addressing Not usable Based Indexed Addressing Data Memory Addressing of PD780826A Special Function Register (SFR) 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Register Addressing Short Direct Addressing F7E0H F7DFH Expansion RAM 480 x 8 bits (shared with DCAN) F600H F5FFH C000H BFFFH Not usable Internal Mask ROM 49152 x 8 bits 0000H Note: In the expansion RAM between F600H and F7DFH it is not possible to do code execution. User's Manual U16504EE1V1UD00 59 Chapter 3 CPU Architecture Figure 3-7: FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FB00H FAFFH FA80H FA7FH FA64H FA63H Not usable LCD Display RAM 28 x 4 bits Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing Data Memory Addressing of PD780828A Special Function Register (SFR) 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Register Addressing Short Direct Addressing Not usable F7E0H F7DFH Expansion RAM 480 x 8 bits (shared with DCAN) F600H F5FFH F400H F3FFH F000H EFFFH Expansion RAM 512 x 8 bits Expansion RAM 1024 x 8 bits Internal Mask ROM 61440 x 8 bits 0000H Notes: 1. In the expansion RAM between F000H and F3FFH it is possible to do code execution. 2. In the expansion RAM between F400H and F7DFH it is not possible to do code execution. 60 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture Figure 3-8: FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FB00H FAFFH FA80H FA7FH FA64H FA63H Not usable LCD Display RAM 28 x 4 bits Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing Data Memory Addressing of PD78F0828A Special Function Register (SFR) 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Register Addressing Short Direct Addressing Not usable F7E0H F7DFH Expansion RAM 480 x 8 bits (shared with DCAN) F600H F5FFH Expansion RAM 1536 x 8 bits F000H EFFFH EE00H EDFFH Flash EEPROM 60928 x 8 bits 0000H Not usable Notes: 1. In the expansion RAM between F000H and F5FFH it is possible to do code execution. 2. In the expansion RAM between F600H and F7DFH it is not possible to do code execution. User's Manual U16504EE1V1UD00 61 Chapter 3 CPU Architecture 3.2 Processor Registers The PD780828A Subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses, and stack memory. The control registers consist of a program counter, a program status word and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-9: 15 Program Counter Configuration 0 PC (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-10: 7 IE Z Program Status Word Configuration 0 RBS1 AC RBS0 0 ISP CY 62 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to interrupt disabled (DI) status. All interrupts except non-maskable interrupt are disabled. When 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledge is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE is reset to (0) upon DI instruction execution or interrupt request acknowledgement and is set to (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledge able maskable vectored interrupts. When 0, acknowledgment of the vectored interrupt request specified to low-order priority with the priority specify flag registers (PR0L, PR0H, and PR1L) is disabled. Whether an actual interrupt request is acknowledged or not is controlled with the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shiftout value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. User's Manual U16504EE1V1UD00 63 Chapter 3 CPU Architecture (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal highspeed RAM area can be set as the stack area. Figure 3-11: 15 Stack Pointer Configuration 0 SP The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 3-12 and 3-13. Caution: Since RESET input makes SP contents indeterminate, be sure to initialize the SP before instruction execution. Figure 3-12: Data to be Saved to Stack Memory Interrupt and BRK Instruction SP SP _ 3 SP _ 3 PC7 to PC0 PC15 to PC8 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 PSW PUSH rp Instruction CALL, CALLF, and CALLT Instruction SP SP _ 2 SP _ 2 SP _ 1 SP Register Pair Lower Register Pair Upper SP SP _ 2 SP _ 2 SP _ 1 SP Figure 3-13: Data to be Reset to Stack Memory RETI and RETB Instruction POP rp Instruction RET Instruction SP SP + 1 SP SP + 2 Register Pair Lower Register Pair Upper SP SP SP + 1 SP + 2 PC7 to PC0 PC15 to PC8 SP SP + 1 SP + 2 SP SP + 3 PC7 to PC0 PC15 to PC8 PSW 64 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture 3.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL). They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank. Figure 3-14: General Register Configuration (a) Absolute Name 16-Bit Processing 8-Bit Processing R7 FEFFH BANK0 FEF8H RP3 R6 R5 BANK1 FEE0H RP1 R2 R1 BANK3 FEE0H 15 0 7 0 RP0 R0 RP2 R4 R3 BANK2 FEE8H (b) Function Name 16-Bit Processing FEFFH H BANK0 FEF8H HL L D BANK1 FEF0H BC C A BANK3 FEE0H 15 0 7 0 AX X DE E B BANK2 FEE8H 8-Bit Processing User's Manual U16504EE1V1UD00 65 Chapter 3 CPU Architecture 3.2.3 Special function register (SFR) Unlike a general register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function registers can be manipulated in a similar way as the general registers, by using operation, transfer, or bit-manipulate instructions. The special function registers are read from and written to in specified manipulation bit units (1, 8, and/or 16) depending on the register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). When addressing an address, describe an even address. Table 3-5, "Special Function Register List," on page 67 gives a list of special function registers. The meaning of items in the table is as follows. * Symbol The assembler software RA78K0 translates these symbols into corresponding addresses where the special function registers are allocated. These symbols should be used as instruction operands in the case of programming. * R/W This column shows whether the corresponding special function register can be read or written. R/W : Both reading and writing are enabled. R : The value in the register can read out. A write to this register is ignored. W : A value can be written to the register. Reading values from the register is impossible. * Manipulation The register can be manipulated in bit units. * After reset The register is set to the value immediately after the RESET signal is input. 66 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture Table 3-5: Address FF00H FF01H FF02H FF03H FF04H FF05H FF06H FF08H FF09H FF12H FF13H FF18H FF19H FF1BH FF1FH FF20H FF22H FF23H FF24H FF25H FF26H FF28H FF29H FF30H FF33H FF34H FF36H FF38H FF39H FF40H FF41H FF42H FF48H FF49H FF50H FF51H FF53H FF54H FF58H FF59H FF65H Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 8 Port 9 8-bit timer register 50 8-bit timer register 51 Compare register 50 Compare register 51 A/D conversion result register Serial I/O shift register 30 Port mode register 0 Port mode register 2 Port mode register 3 Port mode register 4 Port mode register 5 Port mode register 6 Port mode register 8 Port mode register 9 SFR Name Special Function Register List (1/3) Symbol P0 P1 P2 P3 P4 P5 P6 P8 P9 TM50 TM51 CR50 CR51 ADCR1 SIO30 PM0 PM2 PM3 PM4 PM5 PM6 PM8 PM9 PU0 PU3 PU4 PU6 PU8 PU9 CKS WTM WDCS EGP EGN FLPMC PF3 PF4 PF8 PF9 TMC2 R/W R/W R R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Manipulation Bit Unit 1-bit x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 8-bit 16-bit x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x After Reset 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH FFH FFH FFH FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 08H 08H 00H 00H 00H 00H 00H Pull-up resistor option register 0 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 6 Pull-up resistor option register 8 Pull-up resistor option register 9 Clock output select register Watch timer mode register Watchdog timer clock selection register Ext. INT rising edge enable register Ext. INT falling edge enable register Flash programming mode control register Port function register 3 Port function register 4 Port function register 8 Port function register 9 16-bit timer mode control register 2 Self-programming and oscillation control register SPOC User's Manual U16504EE1V1UD00 67 Chapter 3 CPU Architecture Table 3-5: Address FF66H FF67H FF68H FF69H FF6AH FF6BH FF6CH FF6DH FF6EH FF6FH FF70H FF71H FF74H FF75H FF78H FF79H FF7BH FF7CH FF90H FF92H FF93H FF98H FF99H FF9AH FF9BH FFA0H FFA1H FFA2H FFA3H FFA8H FFA9H FFAAH FFABH FFB0H FFB1H FFB2H FFB3H FFB4H FFB5H FFB6H FFB7H FFB8H SFR Name Prescaler mode register 2 Capture/Compare control register 2 16-bit timer/counter register 2 16-bit capture register 20 16-bit capture register 21 16-bit capture register 22 8-bit timer mode control register 50 Timer clock selection register 50 8-bit timer mode control register 51 Timer clock selection register 51 8-bit timer mode control register 52 Timer clock selection register 52 8-bit timer register 52 Compare register 52 LCD display mode register LCD display control register LCD-C/D emulation register A/D converter mode register 1 Analog channel select register 1 Power fail comparator mode register Power fail comparator threshold register UART operation mode register UART receive status register Baud rate generator control register Transmit shift register Receive buffer register Serial mode register SIO30 Serial I/O shift register SIO31 Serial mode register SIO31 2-wire/3-wire mode switch register CAN control register Transmit control register Received message register Redefinition control register CAN error status register Transmit error counter Receive error counter Message count register Bit rate prescaler Special Function Register List (2/3) Symbol PRM2 CRC2 TM2 CR20 CR21 CR22 TMC50 TCL50 TMC51 TCL51 TMC52 TCL52 TM52 CR52 LCDM LCDC LCDTM ADM1 ADS1 PFM PFT ASIM0 ASIS0 BRGC0 TXS0 RXB0 CSIM30 SIO31 CSIM31 SIOSWI CANC TCR RMES REDEF CANES TEC REC MCNT BRPRS R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R R/W R/W R/W W R/W R/W R/W R/W R/W R R/W W R R/W R/W R/W R/W R/W R/W R R/W R/W R R R/W R/W Manipulation Bit Unit 1-bit x x x x x x x x x x x x x 8-bit 16-bit x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x After Reset 00H 00H 0000H 0000H 0000H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH FFH 00H 00H 00H 00H 01H 00H 00H 00H 00H 00H 00H 00H 3FH 68 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture Table 3-5: Address FFB9H FFBAH FFBBH FFBDH FFBFH FFC0H FFC1H FFC2H FFC3H FFC4H FFC5H FFC6H FFC7H FFC8H FFC9H FFCAH FFCBH FFCCH FFCDH FFCEH FFCFH FFE0H FFE1H FFE2H FFE4H FFE5H FFE6H FFE8H FFE9H FFEAH FFF0H FFF4H FFF9H FFFAH FFFBH SFR Name Synchronous control register 0 Synchronous control register 1 Mask control register Meter C/D prescaler switch register 8-bit timer mode control register Sound generator control register Sound generator amplitude register Sound generator buzzer control register Motor 1 compare register Motor 1 compare register Motor 2 compare register Motor 2 compare register Motor 3 compare register Motor 3 compare register Motor 4 compare register Motor 4 compare register Port mode control register Compare control register 1 Compare control register 2 Compare control register 3 Compare control register 4 Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Priority order specified flag 0L Priority order specified flag 0H Priority order specified flag 1L Memory size switching register Internal expansion RAM size switching register Watchdog timer mode register Oscillation stabilisation time register Processor clock control register Special Function Register List (3/3) Symbol SYNC0 SYNC1 MASKC SMSWI MCNTC SGCR SGAM SGBR MCMP10 MCMP11 MCMP20 MCMP21 MCMP30 MCMP31 MCMP40 MCMP41 PMC MCMPC1 MCMPC2 MCMPC3 MCMPC4 IF0L IF0H IF1L MK0L MK0H MK1L PR0L PR0H PR1L IMS IXS WDTM OSTS PCC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Manipulation Bit Unit 1-bit x x x x x x x x x x x x x 8-bit 16-bit x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x After Reset 18H 0EH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH FFH FFH FFH FFH FFH CFH Note 00H 04H 04H Note: The values after reset depend on the product (see Table 23-4, "Values when the Internal Expansion RAM Size Switching Register is Reset," on page 389). User's Manual U16504EE1V1UD00 69 Chapter 3 CPU Architecture 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. However, when a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing. (For details of instructions, refer to 78K/0 User's Manual - Instructions (U12326E). 3.3.1 Relative addressing The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. Figure 3-15: 15 PC + 15 a 8 7 S 6 Relative Addressing 0 ... PC indicates the start address of the instruction after the BR instruction. 0 jdisp8 15 PC 0 When S = 0, all bits of a are 0. When S = 1, all bits of a are 1. 70 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture 3.3.2 Immediate addressing Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL!addr16 or BR!addr16 or CALLF!addr11 instruction is executed. CALL!addr16 and BR!addr16 instructions can branch to all the memory space. CALLF!addr11 instruction branches to the area from 0800H to 0FFFH. Figure 3-16: Immediate Addressing (a) In the case of CALL!addr16 and BR!addr16 instructions 7 CALL or BR Low Addr. High Addr. 0 15 PC 87 0 (b) In the case of CALLF!addr11 instruction 76 fa10-8 fa7-0 4 3 0 CALLF 15 PC 0 0 0 0 11 10 1 87 0 User's Manual U16504EE1V1UD00 71 Chapter 3 CPU Architecture 3.3.3 Table indirect addressing Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory space. Figure 3-17: 7 Operation Code 1 6 1 5 Table Indirect Addressing 1 ta4-0 0 1 15 Effective Address 0 0 0 0 0 0 10 8 0 7 0 6 5 10 0 7 Memory (Table) 0 Low Addr. Effective Address+1 High Addr. 15 PC 8 7 0 72 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture 3.3.4 Register addressing Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. Figure 3-18: 7 rp A Register Addressing 07 X 0 15 PC 8 7 0 User's Manual U16504EE1V1UD00 73 Chapter 3 CPU Architecture 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed. Of the PD780828A Subseries instruction words, the following instructions employ implied addressing. Table 3-6: Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Implied Addressing Register to be Specified by Implied Addressing A register for multiplicant and AX register for product storage AX register for dividend and quotient storage A register for storage of numeric values which become decimal correction targets A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. Description example In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. 74 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture 3.4.2 Register addressing The general register is accessed as an operand. The general register to be accessed is specified with register bank select flags (RBS0 and RBS1) and register specify code (Rn, RPn) in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. Operand format Table 3-7: Identifier r rp Register Addressing Description X, A, C, B, E, D, L, H AX, BC, DE, HL `r' and `rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well as absolute names (R0 to R7 and RP0 to RP3). Description example Figure 3-19: Register Addressing (a) MOV A, C; when selecting C register as r Operation code 01100010 Register specify code (b) INCW DE; when selecting DE register pair as rp Operation code 10000100 Register specify code User's Manual U16504EE1V1UD00 75 Chapter 3 CPU Architecture 3.4.3 Direct addressing The memory indicated by immediate data in an instruction word is directly addressed. Operand format Table 3-8: Identifier addr16 Direct addressing Description Label or 16-bit immediate data Description example MOV A, !0FE00H; when setting !addr16 to FE00H Figure 3-20: Direct addressing Operation code 10001110 00000000 11111110 OP code 00H FEH 76 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture 3.4.4 Short direct addressing The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied to is the 256-byte space, from FE20H to FF1FH. An internal high-speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the SFR area. In this area, ports which are frequently accessed in a program, a compare register of the timer/event counter, and a capture register of the timer/event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to Figure 3-21 below. Operand format Table 3-9: Identifier saddr saddrp Short direct addressing Description Label of FE20H to FF1FH immediate data Label of FE20H to FF1FH immediate data (even address only) Figure 3-21: Short direct addressing (a) Description example MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H. Operation code 00010001 00110000 01010000 OP code 30H (saddr-offset) 50H (immediate data) (b) Illustration 7 OP code saddr-offset 0 Short Direct Memory 15 Effective Address 1 1 1 1 1 1 1 87 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 User's Manual U16504EE1V1UD00 77 Chapter 3 CPU Architecture 3.4.5 Special function register (SFR) addressing The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing. Operand format Table 3-10: Identifier sfr sfrp Special-function register name 16-bit manipulatable special-function register name (even address only) Special-Function Register (SFR) Addressing Description Figure 3-22: Special-Function Register (SFR) Addressing (a) Description example MOV PM0, A; when selecting PM0 (FE20H) as sfr Operation code 11110110 00100000 OP code 20H (sfr-offset) (b) Illustration 7 OP code sfr-offset 0 SFR 15 Effective Address 1 1 1 1 1 1 1 87 1 0 78 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture 3.4.6 Register indirect addressing The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces. Operand format Table 3-11: Identifier - Register indirect addressing Description [DE], [HL] Figure 3-23: Register indirect addressing (a) Description example MOV A, [DE]; when selecting [DE] as register pair Operation code 10000101 (b) Illustration 16 DE D 87 E Memory address specified by register pair DE 0 The contents of addressed memory are transferred 7 Memory 0 7 A 0 User's Manual U16504EE1V1UD00 79 Chapter 3 CPU Architecture 3.4.7 Based addressing 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. Operand format Table 3-12: Identifier Based addressing Description [HL + byte] Figure 3-24: Based addressing description example MOV A, [HL + 10H]; when setting byte to 10H Operation code 10101110 00010000 80 User's Manual U16504EE1V1UD00 Chapter 3 CPU Architecture 3.4.8 Based indexed addressing The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1). Addition is performed by expanding the contents of the B or C register as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. Operand format Table 3-13: Identifier Based indexed addressing Description [HL + B], [HL + C] Figure 3-25: In the case of MOV A, [HL + B] Based indexed addressing description example Operation code 10101011 User's Manual U16504EE1V1UD00 81 Chapter 3 CPU Architecture 3.4.9 Stack addressing The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only. Figure 3-26: In the case of PUSH DE Stack addressing description example Operation code 10110101 82 User's Manual U16504EE1V1UD00 Chapter 4 4.1 Port Functions Port Functions The PD780828A Subseries units incorporate five input ports and thirty-eight input/output ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as onchip hardware input/output pins. Figure 4-1: Port Types P00 Port 0 P03 P60 Port 6 P65 P14 P10 Port 1 P20 P80 Port 2 Port 8 P27 P87 P34 Port 3 P37 P40 P90 Port 4 Port 9 P47 P97 P50 Port 5 P57 User's Manual U16504EE1V1UD00 83 Chapter 4 Port Functions Table 4-1: Input/ Output Pin Name P00 Input/ Output P01 P02 P03 Input P10-P14 P20 P21 P22 Output P23 P24 P25 P26 P27 P34 Input/ Output P35 P36 P37 Port 2 8-bit output only port Pin Input/Output Types (1/2) Function Alternate Function INTP0 INTP1 INTP2 CCLK AN10-AN17 SM11 SM12 SM13 SM14 SM21 SM22 SM23 SM24 TI50/TO50/S27 Input Input Input Input Hi-z After Reset Input Input Input Input Input Output Port 0 4-bit input/output port Input/output mode can be specified bit-wise If used an input port, a pull-up resistor can be connected by software bit-wise Port 1 5-bit input only port Port 3 4 bit input/output port Input/output mode can be specified bit-wise SCK30/S26 S030/S25 SI30/S24 Input/ Output Port 4 8-bit input/output port P40-P47 Input/output mode can be specified bit-wise S0-S7 This port can be used as a segment signal output port or an I/O port, in an 8-bit unit setting the port function P50 P51 P52 SM31 SM32 SM33 Port 5 8-bit output only port SM34 SM41 SM42 SM43 SM44 SGOF-SGO SGOA-PCL Port 6 6-bit input/output port Input/output mode can be specified bit-wise RXD0 TXD0 TI20 TI21 Input Output P53 P54 P55 P56 P57 P60 P61 Hi-z Input/ Output P62 P63 P64 P65 Input 84 User's Manual U16504EE1V1UD00 Chapter 4 Table 4-1: Input/ Output Pin Name Port Functions Pin Input/Output Types (2/2) Function Alternate Function After Reset Input/ Output Port 8 8-bit input/output port Input/output mode can be specified bit-wise P80-P87 If used an input port, a pull-up resistor can be connected by S15-S8 software This port can be used as a segment signal output port or an I/O port, in an 1-bit units by setting the port function P90 P91 P92 Port 9 8-bit input/output port Input/output mode can be specified bit-wise This port can be used as a segment signal output port or an I/O port, in an 1-bit units by setting the LCD control register TI22/S23 TO51/TI51/S22 TP0/S21 SCK31/S20 SO31/SIO31/S19 SI31/S18 S17 S16 Input Input/ Output P93 P94 P95 P96 P97 Input User's Manual U16504EE1V1UD00 85 Chapter 4 Port Functions 4.2 Port Configuration A port consists of the following hardware: Table 4-2: Item Control register Port Pull-up resistor PD78F0828A Port Configuration Configuration Port mode register (PMm: m = 0, 2 to 6, 8, 9) Pull-up resistor option register (PUm: m = 0, 3, 4, 6, 8, 9) Port function register (PFm: m = 3, 4, 8, 9) Total: 79 ports Mask ROM versions Total: 38 pins Total: 38 pins 86 User's Manual U16504EE1V1UD00 Chapter 4 4.2.1 Port 0 Port Functions Port 0 is an 4-bit input/output port with output latch. P00 to P03 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (PM0). When P00 to P03 pins are used as input pins, a pull-up resistor can be connected to them bit-wise with the pull-up resistor option register (PUm). Dual-function includes external interrupt request input and the external clock input for the DCAN peripheral. RESET input sets port 0 to input mode. Figure 4-2 shows block diagram of port 0. Caution: Because port 0 also serves for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. Thus, when the output mode is used, set the interrupt mask flag to 1, in order to avoid an factorized interrupt. Figure 4-2: P00 to P03 Configurations VDD WRPUO PU0 RD P-ch Selector Internal bus WRPORT Output Latch (P00 to P03) P00/INTP0, P01/INTP1, P02/INTP2, P03/CCLK WRPM PM00 to PM03 Remarks: 1. PU0 2. PM 3. RD 4. WR : Pull-up resistor option register : Port mode register : Port 0 read signal : Port 0 write signal User's Manual U16504EE1V1UD00 87 Chapter 4 4.2.2 Port 1 Port Functions Port 1 is an 5-bit input only port. Dual-functions include an A/D converter analog input. Figure 4-3 shows a block diagram of port 1. Figure 4-3: P10 to P14 Configurations RD Internal bus P10/ANI0 to P14/ANI4 Remark: RD: Port 1 read signal 88 User's Manual U16504EE1V1UD00 Chapter 4 4.2.3 Port 2 Port Functions Port 2 is an 8-bit output port with output latch. P20 to P27 goes into a high impedance state when the port mode register 2 is set to 1. Dual-function includes meter control PWM output. RESET input sets port 2 to high-impedance state. Figure 4-4 shows a block diagram of port 2. Caution: When port 2 is set to 1, the read back from output latch operation is enabled. When port 2 is set to 0, the read back from output latch operation is disabled. Figure 4-4: P20 to P27 Configurations RD Internal bus WRPORT Output Latch (P20 to P27) Note 1 P20/SM11 to P23/SM14 P24/SM21 to P27/SM24 WRPM PM20 to PM27 Dual Function Note 2 Remarks: 1. PM 2. RD 3. WR : Port mode register : Port 2 read signal : Port 2 write signal Notes: 1. Set output latch to 0 when dual function shall be applied to output. 2. Disable dual function when the content of the output latch shall be applied to output. User's Manual U16504EE1V1UD00 89 Chapter 4 4.2.4 Port 3 Port Functions Port 3 is an 4-bit input/output port with output latch. P34 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3). When P34 to P37 are used as input pins, pull-up resistors can be connected bit-wise with the pull-up resistor option register (PU3). Dual-function includes timer input/output, serial interface data input/output, serial interface clock input/output and segment signal output of the LCD controller/driver. RESET input sets port 3 to input mode. Figure 4-5 shows a block diagram of port 3. Caution: When used as segment lines, set the port function (PF3) according to its function. Figure 4-5: P34 to P37 Configurations RD Selector Internal bus WRPORT Output Latch Note 1 (P34 to P37) P34/TO50/TI50/S27 P35/SCK3/S26 P36/SO3/S25 P37/SI3/S24 WRPM PM34 to PM37 Dual Function Note 2 Remarks: 1. PM 2. RD 3. WR : Port mode register : Port 3 read signal : Port 3 write signal Notes: 1. Set output latch to 0 when dual function shall be applied to output. 2. Disable dual function when the comment of the output latch shall be applied to output. 90 User's Manual U16504EE1V1UD00 Chapter 4 4.2.5 Port 4 Port Functions This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with the port mode register 4. When P40 to P47 are used as input pins, pull-up resistors can be connected bit-wise with the pull-up resistor option register (PU4). These pins are dual function pin and serve as segment signal output of LCD controller/driver. RESET input sets the input mode. The port 4 block diagram is shown in Figure 4-6. Caution: When used as segment lines, set the port function (PF4) according to its function. Figure 4-6: P40 to P47 Configurations RD Selector WRPORT Output Latch (P40 to P47) Internal bus Note 1 P40/S7 to P47/S0 WRPM PM40 to PM47 Dual Function Note 2 Remarks: 1. PUO : Pull-up resistor option register 2. PM 3. RD 4. WR : Port mode register : Port 4 read signal : Port 4 write signal Notes: 1. Set output latch to 0 when dual function shall be applied to output. 2. Disable dual function when the comment of the output latch shall be applied to output. User's Manual U16504EE1V1UD00 91 Chapter 4 4.2.6 Port 5 Port Functions Port 5 is an 8-bit output port with output latch. P50 to P57 goes into a high-impedance state when the port mode register 5 is set to 1. The dual-function includes meter control PWM output. RESET input sets port 5 to high-impedance state. Figure 4-7 shows a block diagram of port 5. Caution: When port 5 is set to 1, the read back from output latch operation is enabled. When port 5 is set to 0, the read back from output latch operation is disabled. Figure 4-7: P50 to P57 Configurations RD WRPORT Output Latch (P50 to P57) Internal bus Note 1 P50/SM31 to P53/SM34 P54/SM41 to P57/SM44 WRPM PM50 to PM57 Note 2 Dual Function Remarks: 1. PM 2. RD 3. WR : Port mode register : Port 5 read signal : Port 5 write signal Notes: 1. Set output latch to 0 when dual function shall be applied to output. 2. Disable dual function when the comment of the output latch shall be applied to output. 92 User's Manual U16504EE1V1UD00 Chapter 4 4.2.7 Port 6 Port Functions Port 6 is an 6-bit input/output port with output latch. P60 to P65 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). When P62 to P65 are used as input pins, pull-up resistors can be connected bit-wise with the pull-up resistor option register (PU6). The dual-function includes the asynchronous serial interface receive/transmit, the timer capture input of TM2 and the sound generator output. RESET input sets port 6 to input mode. Figure 4-8 shows block diagrams of port 6. Figure 4-8: P60 to P65 Configurations RD Selector Internal bus WRPORT Output Latch P60 to P65 Note P60/SGOF/SGO, P61/SGOA/PCL, P62/RXD0, P63/TXD0, P64/TI20, P65/TI21 WRPM PM60 to PM65 Remarks: 1. PM 2. RD 3. WR : Port mode register : Port 6 read signal : Port 6 write signal Note: Set output latch to 0 when dual function shall be applied to output. Caution: The pull-up option is not available for P60 and P61. User's Manual U16504EE1V1UD00 93 Chapter 4 4.2.8 Port 8 Port Functions This is a 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with a port mode register 8. When P80 to P87 are used as input pins, pull-up resistors can be connected bit-wise with the pull-up resistor option register (PU8). Dual-function includes segment signal output of LCD controller/driver. RESET input sets the input mode. Port 8 block diagram is shown in Figure 4-9. Caution: When used as segment lines, set the port function PF8 according to its functions. Figure 4-9: P80 to P87 Configurations RD Selector Internalbus WRPORT Output Latch Note 1 (P80 to P87) P80/S8 P87/S15 WRPM PM80 to PM87 Dual Function Note 2 Remarks: 1. PM 2. RD 3. WR : Port mode register : Port 7 read signal : Port 7 write signal Notes: 1. Set output latch to 0 when dual function shall be applied to output. 2. Disable dual function when the comment of the output latch shall be applied to output. 94 User's Manual U16504EE1V1UD00 Chapter 4 4.2.9 Port 9 Port Functions This is a 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with the port mode register 9. When P90 to P97 are used as input pins, pull-up resistors can be connected bit-wise with the pull-up resistor option register (PU9). These pins are dual function pin and serve as segment signal output of LCD controller/driver. RESET input sets the input mode. The port 9 block diagram is shown in Figure 4-10. Caution: See port 4 with change to PF4. Figure 4-10: P90 to P97 Configurations RD Selector WRPORT Output Latch (P90 to P97) Note 1 Internal bus P90/TI22/S23, P91/TO51/TI51/S22, P92/TP0/S21, P93/S20/SCK31, P94/S19/SO31/SIO31, P95/S18/SI31, P96/S17, P97/S16 WRPM PM90 to PM97 Dual Function Note 2 Remarks: 1. PUO : Pull-up resistor option register 2. PM 3. RD 4. WR : Port mode register : Port 13 read signal : Port 13 write signal Notes: 1. Set output latch to 0 when dual function shall be applied to output. 2. Disable dual function when the comment of the output latch shall be applied to output. User's Manual U16504EE1V1UD00 95 Chapter 4 Port Functions 4.3 Port Function Control Registers The following three types of registers control the ports. * Port mode registers (PM0, PM2 to PM6, PM8, PM9) * Pull-up resistor option register (PU0, PU3, PU4, PU6, PU8, PU9) * Port function registers (PF3, PF4, PF8, PF9) (1) Port mode registers (PM0, PM2 to PM6, PM8, PM9) These registers are used to set port input/output in 1-bit units. PM0, PM2 to PM6, PM8 and PM9 are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch according to the function. Cautions: 1. Pins P10 to P14 are input-only pins. 2. As port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 96 User's Manual U16504EE1V1UD00 Chapter 4 Figure 4-11: Port Functions Port Mode Register Format 7 PM0 1 6 1 5 1 4 1 3 PM03 2 PM02 1 PM01 0 PM00 R/W Address R/W FF20H After Reset FFH After Reset FFH After Reset FFH After Reset FFH After Reset FFH After Reset FFH 7 PM3 PM37 6 PM36 5 PM35 4 PM34 3 1 2 1 1 1 0 1 R/W Address R/W FF23H 7 PM4 PM47 6 PM46 5 PM45 4 PM44 3 PM43 2 PM42 1 PM41 0 PM40 R/W Address R/W FF24H 7 PM6 1 6 1 5 PM65 4 PM64 3 PM63 2 PM62 1 PM61 0 PM60 R/W Address R/W FF26H 7 PM8 PM87 6 PM86 5 PM85 4 PM84 3 PM83 2 PM82 1 PM81 0 PM80 R/W Address R/W FF28H 7 PM9 PM97 6 PM96 5 PM95 4 PM94 3 PM93 2 PM92 1 PM91 0 PM90 R/W Address R/W FF29H PMmn 0 1 PMmn Pin Input/Output Mode Selection (m = 0, 3, 4, 6, 8, 9; n = 0 - 7) Output mode (output buffer ON) Input mode (output buffer OFF) 7 PM2 PM27 6 PM26 5 PM25 4 PM24 3 PM23 2 PM22 1 PM21 0 PM20 R/W Address R/W FF22H After Reset FFH After Reset FFH 7 PM5 PM57 6 PM56 5 PM55 4 PM54 3 PM53 2 PM52 1 PM51 0 PM50 R/W Address R/W FF25H PMmn 0 1 PMmn Pin Output Buffer Selection (m = 2, 5; n = 0 - 7) Output mode (output buffer ON) Hi-Z mode (output buffer OFF) User's Manual U16504EE1V1UD00 97 Chapter 4 (2) Port Functions Pull-up resistor option register (PU0, PU3, PU4, PU6, PU8, PU9) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUm (m = 0, 3, 4, 6, 8, 9). No on-chip pull-up resistors can be used to the bits set to the output mode, irrespective of PU setting. PUm is set with an 1-bit or an 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 4-12: Pull-Up Resistor Option Register (PUm) Format 7 PU0 0 6 0 5 0 4 0 3 PU03 2 PU02 1 PU01 0 PU00 R/W Address R/W FF30H After Reset 00H After Reset 00H After Reset 00H After Reset 00H After Reset 00H After Reset 00H 7 PU3 PU37 6 PU36 5 PU35 4 PU34 3 0 2 0 1 0 0 0 R/W Address R/W FF33H 7 PU4 PU47 6 PU46 5 PU45 4 PU44 3 PU43 2 PU42 1 PU41 0 PU40 R/W Address R/W FF34H 7 PU6 0 6 0 5 PF65 4 PF64 3 PF63 2 PF62 1 0 0 0 R/W Address R/W FF36H 7 PU8 PU87 6 PU86 5 PU85 4 PU84 3 PU83 2 PU82 1 PU81 0 PU80 R/W Address R/W FF38H 7 PU9 PU97 6 PU96 5 PU95 4 PU94 3 PU93 2 PU92 1 PU91 0 PU90 R/W Address R/W FF39H PUmn 0 1 PUmn Pin Internal Pull-up Resistor Selection (m = 0, 3, 4, 6, 8, 9; n = 0 - 7) On-chip pull-up resistor not used On-chip pull-up resistor used Remark: Caution: The pull-up option is not available for P60 and P61. Once the software can't use pull-up resistors are connected by setting 1 to the pull-up resistor option register, they are not disconnected even in output mode. To switch off the pull-up resistors must be written to the pull-up resistor option register. 98 User's Manual U16504EE1V1UD00 Chapter 4 (3) Port Functions Port function register (PF3, PF4, PF8 and PF9) This register is used to set the LCD segment function of ports 3, 4, 8 and 9. PF3, PF8 and PF9 are set with an 1-bit or 8-bit manipulation instruction. PF4 is set with an 8-bit manipulation instruction. RESET input sets this register to 00H. Figure 4-13: Port Function Register (PF3, PF4, PF8 and PF9) Format 7 PF3 PF37 6 PF36 5 PF35 4 PF34 3 0 2 0 1 0 0 0 R/W Address R/W FF53H After Reset 00H After Reset 00H After Reset 00H After Reset 00H 7 PF4 PF47 6 PF46 5 PF45 4 PF44 3 PF43 2 PF42 1 PF41 0 PF40 R/W Address R/W FF54H 7 PF8 PF87 6 PF86 5 PF85 4 PF84 3 PF83 2 PF82 1 PF81 0 PF80 R/W Address R/W FF58H 7 PF9 PF97 6 PF96 5 PF95 4 PF94 3 PF93 2 PF92 1 PF91 0 PF90 R/W Address R/W FF59H PFmn 0 1 PFmn Port Function Selection (m = 3, 4, 8, 9; n = 0 - 7) Port function LCD segment function Caution: For PF4 it is only allowed to set 00H or FFH. For PF3 only the 4 MSB are relevant. User's Manual U16504EE1V1UD00 99 Chapter 4 Port Functions 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. Caution: In the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 4.4.2 Reading from input/output port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 100 User's Manual U16504EE1V1UD00 Chapter 4 4.4.3 Operations on input/output port Port Functions (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change. Caution: In the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. User's Manual U16504EE1V1UD00 101 [MEMO] User's Manual U16504EE1V1UD00 102 Chapter 5 Clock Generator 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillators is available. (1) Main system clock oscillator This circuit oscillates at frequencies of 4 to 8.38 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register. 5.2 Clock Generator Configuration The clock generator consists of the following hardware. Table 5-1: Item Control register Oscillator Clock Generator Configuration Configuration Processor clock control register (PCC) Main system clock oscillator Subsystem clock oscillator Figure 5-1: Block Diagram of Clock Generator Prescaler X1 Main System Clock Oscillator fX fX fX 2 Clock to peripheral hardware fX 24 Prescaler fX 22 fX 23 X2 STOP Selector Standby Control Circuit Note CPU Clock (fCPU) Note: The Standby function is described in the Chapter 21 "Standby Function" on page 373". User's Manual U16504EE1V1UD00 103 Chapter 5 Clock Generator 5.3 Clock Generator Control Register The clock generator is controlled by the processor clock control register (PCC). (1) Processor clock control register (PCC) The PCC selects a CPU clock and the division ratio at the CPU clock. The PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the PCC to 04H. Figure 5-2: Processor Clock Control Register Format 7 PCC 0 6 0 5 0 4 0 3 0 2 PCC2 1 PCC1 0 PCC0 R/W Address R/W FFFBH After Reset 04H PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 PCC0 0 1 0 1 0 CPU Clock Selection (fCPU) fX fX /2 fX /22 fX /23 fX /24 Setting prohibited Other than above Caution: Remark: Bit 3 to Bit 7 must be set to 0. fX: Main system clock oscillation frequency 104 User's Manual U16504EE1V1UD00 Chapter 5 Clock Generator 5.4 System Clock Oscillator 5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, the clock signal is supplied to the X1 pin and the X2 pin has to be left open. Figure 5-3 shows an external circuit of the main system clock oscillator. Figure 5-3: External Circuit of Main System Clock Oscillator (a) Crystal and ceramic oscillation IC X2 X1 Crystal or Ceramic Resonator (b) External clock Open X2 External Clock PD74HCU04 X1 Caution: Do not execute the STOP instruction if an external clock is input. This is because when the STOP instruction is used the main system clock operation stops and the X2 pin is connected to VDD1 via a pull-up resistor. User's Manual U16504EE1V1UD00 105 Chapter 5 Clock Generator Figure 5-4: Examples of Oscillator with Bad Connection (1/3) (a) Wiring of connection circuits is too long IC X2 X1 (b) A signal line crosses over oscillation circuit lines PORTn (n = 0 to 10, 12, 13) IC X2 X1 106 User's Manual U16504EE1V1UD00 Chapter 5 Figure 5-4: Clock Generator Examples of Oscillator with Bad Connection (2/3) (c) Changing high current is too near a signal conductor IC X2 X1 High Current (d) Current flows through the grounding line of the oscillator (potential at points A, B, and C fluctuate) VDD Pnm IC X2 X1 A B High Current C User's Manual U16504EE1V1UD00 107 Chapter 5 Clock Generator Figure 5-4: Examples of Oscillator with Bad Connection (3/3) (e) Signals are fetched IC X2 X1 108 User's Manual U16504EE1V1UD00 Chapter 5 Clock Generator 5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. * Main system clock fX * CPU clock fCPU * Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC). (a) Upon generation of RESET signal, the lowest speed mode of the main system clock (4 s when operated at 8.0 MHz) is selected (PCC = 04H). Main system clock oscillation stops while low level is applied to RESET pin. (b) With the main system clock selected, one of the five CPU clock stages (fX, fX/2, fX/22, fX/23 or fX/24) can be selected by setting the PCC. (c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. User's Manual U16504EE1V1UD00 109 Chapter 5 Clock Generator 5.6 Changing System Clock and CPU Clock Settings 5.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2) of the processor clock control register (PCC). The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the pre-switchover clock for several instructions (see Table 5-2). Table 5-2: Set Values after Switchover PCC2 PCC1 PCC0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Maximum Time Required for CPU Clock Switchover Set Values before Switchover PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 8 instructions 16 instructions 16 instructions 16 instructions 16 instructions 8 instructions 8 instructions 8 instructions 4 instructions 4 instructions 2 instructions 2 instructions 2 instructions 1 instruction 1 instruction 1 instruction 1 instruction 4 instructions 4 instructions 2 instructions 110 User's Manual U16504EE1V1UD00 Chapter 5 Clock Generator 5.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 5-5: System Clock and CPU Clock Switching VDD RESET Interrupt Request Signal System Clock CPU Clock fX Minimum Speed Operation fX Maximum Speed Operation Wait (16.3 ms: 8.0 MHz) Internal Reset Operation (1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation stabilization time (217/fX) is secured automatically. After that, the CPU starts executing the instruction at the minimum speed of the main system clock (4 s when operated at 8.0 MHz). (2) After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds, the processor clock control register (PCC) is rewritten and the maximum-speed operation is carried out. User's Manual U16504EE1V1UD00 111 [MEMO] User's Manual U16504EE1V1UD00 112 Chapter 6 6.1 16-Bit Timer 2 Functions 16-Bit Timer 2 The 16-bit timer 2 (TM2) has the following functions. * Pulse width measurement * Divided output of input pulse * Time stamp function for the DCAN Figure 6-1 shows 16-Bit Timer 2 Block Diagram. Figure 6-1: Timer 2 (TM2) Block Diagram Internal bus Capture pulse control register (CRC2) CRC21CRC20 Prescaler mode register (PRM2) ES21 ES20 ES11 ES10 ES01 ES00 PRM21PRM20 16-bit timer mode control register (TMC2) TMC22 TPOE fx/4 fx/8 fx/32 fx/128 Selector 16-bit timer register (TM2) INTOVF ES21, ES20 TI22/S23/P90 Noise rejection circuit Prescaler 1, 1/2, 1/4, 1/8 Edge detection circuit 16-bit capture register (CR22) INTTM22 16-bit capture register (CR21) INTTM21 16-bit capture register (CR20) INTTM20 ES11, ES10 TI21/P65 Noise rejection circuit Edge detection circuit ES01, ES00 TI20/P64 Noise rejection circuit Edge detection circuit TPO/S21/P92 TPOE Internal bus DCAN (1) Pulse width measurement TM2 can measure the pulse width of an external input signal. (2) Divided output of input pulse The frequency of an input signal can be divided and the divided signal can be output. (3) Timer stamp function for the DCAN An internal signal output of the DCAN-module can be used to build a time stamp function of the system (please refer to the chapter of the DCAN-module). User's Manual U16504EE1V1UD00 113 Chapter 6 16-Bit Timer 2 6.2 16-Bit Timer 2 Configuration Timer 2 consists of the following hardware. Table 6-1: Item Timer register Register Timer 2 Configuration Configuration 16 bits x 1 (TM2) Capture register: 16 bits x 3 (CR20 to CR22) 16 bit timer mode control register (TMC2) Control register Capture pulse control register (CRC2) Prescaler mode register (PRM2) (1) 16-bit timer register (TM2) TM2 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of an input clock. The count value is reset to 0000H in the following case: At RESET input The count value is undefined in the following case: - TMC22 is disabled. Caution: When the timer TM2 is disabled, the value of the timer register TM2 will be undefined. (2) Capture register 20 (CR20) The valid edge of the TI20 pin can be selected as the capture trigger. Setting of the TI20 valid edge is performed by setting of the prescaler mode register (PRM2). When the valid edge of the TI20 is detected, an interrupt request (INTTM20) is generated. CR20 is read by a 16-bit memory manipulation instruction. After RESET input, the value of CR20 is undefined. 114 User's Manual U16504EE1V1UD00 Chapter 6 16-Bit Timer 2 (3) Capture register 21 (CR21) The valid edge of the TI21 pin can be selected as the capture trigger. Setting of the TI21 valid edge is performed by setting of the prescaler mode register (PRM2). When the valid edge of the TI21 is detected, an interrupt request (INTTM21) is generated. CR21 is read by a 16-bit memory manipulation instruction. After RESET input, the value of CR21 is undefined. (4) Capture register 22 (CR22) The valid edge of the TI22 pin can be selected as the capture trigger. Setting of the TI22 valid edge is performed by setting of the prescaler mode register (PRM2). When the valid edge of the TI22 is detected, an interrupt request (INTTM22) is generated. CR22 is read by a 16-bit memory manipulation instruction. After RESET input, the value of CR22 is undefined. User's Manual U16504EE1V1UD00 115 Chapter 6 16-Bit Timer 2 6.3 16-Bit Timer 2 Control Registers The following three types of registers are used to control timer 0. * 16-bit timer mode control register (TMC2) * Capture pulse control register (CRC2) * Prescaler mode register (PRM2) (1) 16-bit timer mode control register (TMC2) This register sets the 16-bit timer operating mode and controls the prescaler output signals. TMC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC2 value to 00H. Figure 6-2: 16-Bit Timer Mode Control Register (TMC2) Format 7 TMC2 0 6 0 5 0 4 0 3 0 <2> TMC22 1 0 <0> TPOE R/W Address R/W FF65H After Reset 00H TMC2 0 1 Timer 2 Operating Mode Selection Operation stop Operation enabled TPOE 0 1 Timer 2 Prescaler Output Control Prescaler signal output disabled Prescaler signal output enabled Cautions: 1. Before changing the operation mode, stop the timer operation (by setting 0 to TMC22). 2. Bit 1 and bits 3 to 7 must be set to 0. 116 User's Manual U16504EE1V1UD00 Chapter 6 16-Bit Timer 2 (2) Capture pulse control register (CRC2) This register specifies the division ratio of the capture pulse input to the 16-bit capture register (CR22) from an external source. CRC2 is set with an 8-bit memory manipulation instruction. RESET input sets CRC2 value to 00H. Figure 6-3: Capture Pulse Control Register (CRC2) Format 7 CRC2 0 6 0 5 0 4 0 3 0 2 0 1 CRC21 0 CRC20 R/W Address R/W FF67H After Reset 00H CRC21 0 0 1 1 CRC20 0 1 0 1 TI22 - Capture Pulse Selection Does not divide capture pulse (TI22) Divides capture pulse by 2 (TI22/2) Divides capture pulse by 4 (TI22/4) Divides capture pulse by 8 (TI22/8) Cautions: 1. Timer operation must be stopped before setting CRC2. 2. Bits 2 to 7 must be set to 0. User's Manual U16504EE1V1UD00 117 Chapter 6 16-Bit Timer 2 (3) Prescaler mode register (PRM2) This register is used to set 16-bit timer (TM2) count clock and valid edge of TI2n (n = 0 to 2) input. PRM2 is set with an 8-bit memory manipulation instruction. RESET input sets PRM2 value to 00H. Figure 6-4: Prescaler Mode Register (PRM2) Format 7 PRM2 ES21 6 ES20 5 ES11 4 ES10 3 ES01 2 ES00 1 PRM21 0 R/W Address FF66H After Reset 00H PRM20 R/W ES21 0 0 1 1 ES20 0 1 0 1 Falling edge Rising edge TI02 Valid Edge Selection Setting prohibited Both falling and rising edges ES11 0 0 1 1 ES10 0 1 0 1 Falling edge Rising edge TI01 Valid Edge Selection Setting prohibited Both falling and rising edges ES01 0 0 1 1 ES00 0 1 0 1 Falling edge Rising edge TI00 Valid Edge Selection Setting prohibited Both falling and rising edges PRM21 0 0 1 1 PRM20 0 1 0 1 Count Clock Selection fX/23 fX/24 fX/25 fX/26 Caution: Timer operation must be stopped before setting PRM2. 118 User's Manual U16504EE1V1UD00 Chapter 6 16-Bit Timer 2 6.4 16-Bit Timer 2 Operations 6.4.1 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the timer input pins by using the 16-bit timer register (TM2). TM2 is used in free-running mode. (1) Pulse width measurement with free-running counter and one capture register (TI20) When the edge specified by the prescaler mode register (PRM2) is input to the TI20 pin, the value of TM2 is taken into 16-bit capture register 20 (CR20) and an external interrupt request signal (INTTM20) is set. Any of three edge specifications can be selected - rising, falling, or both edges - by means of bits 2 and 3 (ES00 and ES01) of PRM2. For valid edge detection, sampling is performed at the count clock selected by PRM2, and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 6-5: Configuration Diagram for Pulse Width Measurement by Using the Free Running Counter fx/23 fx/24 fx/25 fx/26 Selector 16-bit timer register (TM2) INTOVF TI20 16-bit capture register 20 (CR20) INTTM20 Internal bus User's Manual U16504EE1V1UD00 119 Chapter 6 16-Bit Timer 2 Figure 6-6: Timing of Pulse Width Measurement Operation by Using the Free Running Counter and One Capture Register (with Both Edges Specified) t Count clock TM0 count value TI00 pin input Value loaded to CR00 INTTM00 D0 D1 D2 D3 0000H 0001H D0 D1 FFFFH 0000H D2 D3 INTOVF (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t 120 User's Manual U16504EE1V1UD00 Chapter 6 16-Bit Timer 2 (2) Measurement of three pulse widths with the free running counter The 16-bit timer register (TM2) allows simultaneous measurement of the pulse widths of the three signals input to the TI20 to TI22 pins. When the edge specified by bits 2 and 3 (ES00 and ES01) of prescaler mode register (PRM2) is input to the TI20 pin, the value of TM2 is taken into 16-bit capture register 20 (CR20) and an external interrupt request signal (INTTM20) is set. Also, when the edge specified by bits 4 and 5 (ES10 and ES11) of PRM0 is input to the TI21 pin, the value of TM2 is taken into 16-bit capture register 21 (CR21) and an external interrupt request signal (INTTM21) is set. When the edge specified by bits 6 and 7 (ES20 and ES21) of PRM2 is input to the TI22 pin, the value of TM2 is taken into 16-bit capture register 22 (CR22) and external interrupt request signal (INTTM22) is set. Any of three edge specifications can be selected - rising, falling, or both edges - as the valid edges for the TI20 to TI22 pins by means of bits 2 and 3 (ES00 and ES01), bits 4 and 5 (ES10 and ES11), and bits 6 and 7 (ES06 and ES07) of PRM2, respectively. For TI20 pin valid edge detection, sampling is performed at the interval selected by the prescaler mode register (PRM2), and a capture operation is only performed when a valid level is detected twice, thus eliminates the noise of a short pulse width. * Capture operation Capture register operation in capture trigger input is shown. Figure 6-7: Count clock TM2 TI2m Rising edge detection CR2m INTTM2m CR2m Capture Operation with Rising Edge Specified n-3 n-2 n-1 n n+1 n Remark: m = 0 to 2 User's Manual U16504EE1V1UD00 121 Chapter 6 16-Bit Timer 2 Figure 6-8: Timing of Pulse Width Measurement Operation by Free Running Counter (with Both Edges Specified) t Count clock TM2 count value TI2m pin input Value loaded to CR2m INTTM2m TI2n pin input Value loaded to CR2n INTTM2n INTOVF (D1 - D0) x t (10000H - D0 + D2) x t (10000H - D1 + (D2 + 1) x t (D3 - D2) x t D1 D0 D1 D2 D3 0000H 0001H D0 D1 FFFFH 0000H D2 D3 Remark: m = 0 to 2, n = 1, 2 122 User's Manual U16504EE1V1UD00 Chapter 6 16-Bit Timer 2 6.5 16-Bit Timer 2 Precautions (1) Timer start errors An error with a maximum of one clock may occur until counting is started after timer start, because the 16-bit timer register (TM2) can be started asynchronously with the count pulse. Figure 6-9: Count pulse 16-Bit Timer Register Start Timing TM2 count value 0000H 0001H 0002H 0003H 0004H Timer start (2) Capture register data retention timings If the valid edge of the TI2n pin is input during the 16-bit capture register 0m (CR2n) is read, CR2m performs capture operation, but the capture value is not guaranteed. However, the interrupt request flag (INTTM2n) is set upon detection of the valid edge. Figure 6-10: Count pulse TM2 count value Edge input Interrupt request flag Capture read signal CR0n interrupt value X N-3 N-2 Capture Register Data Retention Timing N-1 N N+1 M-3 M-2 M-1 M M+1 M+2 M+3 N N Capture operation Remark: n = 0 to 2 User's Manual U16504EE1V1UD00 123 Chapter 6 16-Bit Timer 2 (3) Valid edge setting Set the valid edge of the TI2m/P3m pin after setting bit 2 (TMC22) of the 16-bit timer mode control register to 0, and then stopping timer operation. Valid edge setting is carried out with bits 2 to 7 (ESm0 and ESm1) of the prescaler mode register (PRM2). Remark: m = 0 to 2 (4) Occurrence of INTTM2n INTTM2n occurs even if no capture pulse exists, immediately after the timer operation has been started (TMC02 of TMC2 has been set to 1) with a high level applied to the input pins TI20 to TI22 of 16-bit timer 2. This occurs if the rising edge (with ESn1 and ESn0 of PRM0 set to 0, 1), or both the rising and falling edges (with ESn1 and ESn0 of PRM2 set to 1, 1) are selected. INTTM2n does not occur if a low level is applied to TI20 to TI22. (5) Timer stop When the timer TM2 is disabled, the value of the timer register will be undefined. 124 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.1 8-Bit Timer/Event Counters 50 and 51 Functions The timer 50 and 51 have the following two modes: * Mode using TM50 and TM51 alone (individual mode) * Mode using the cascade connection (16-bit cascade mode connection). (1) Mode using TM50 and TM51 as 8-bit timers The timer operate as 8-bit timer/event counters. They have the following functions: * Interval timer * External event counter * Square-wave output * PWM output (2) Mode using the cascade connection as 16-bit timer The timer operates as 16-bit timer/event counter. It has the following functions: * Interval timer * External event counter * Square-wave output User's Manual U16504EE1V1UD00 125 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.1.1 8-bit operation modes (1) 8-bit interval timer Interrupts are generated at the present time intervals. Table 7-1: 8-Bit Timer/Event Counter 50 Interval Times Maximum Interval Width 2 11 Minimum Interval Width 23 x 1/fX (1 s) Resolution 2 x 1/fX (1 s) 3 x 1/fX (256 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) 213 x 1/fX (1 s) 215 x 1/fX (4 s) 216 x 1/fX (8 ms) 217 x 1/fX (16 ms) 219 x 1/fX (65 ms) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Table 7-2: 8-Bit Timer/Event Counter 51 Interval Times Maximum Interval Width 212 x 1/fX (512 s) Resolution 1/fX (2 s) 21 x 1/fX (8 s) 23 x 1/fX (16 s) 25 x 1/fX (32 s) 27 x 1/fX (128 s) 212 x 1/fX (512 s) Minimum Interval Width 24 x 1/fX (2 s) 26 x 1/fX (8 s) 27 xx 1/fX (16 s) 28 xx 1/fX (32 s) 210 xx 1/fX (128 s) 212 x 1/fX (512 s) 214 x 1/fX (2 s) 215 x 1/fX (4 s) 216 x 1/fX (8 ms) 218 x 1/fX (32 ms) 220 x 1/fX (131 ms) Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses when operated at fX = 8.0 MHz. 126 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 7-3: 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges Maximum Interval Width 211 x 1/fX (256 s) 213 x 1/fX (1 s) 215 x 1/fX (4 s) 216 x 1/fX (8 ms) 217 x 1/fX (16 ms) 219 x 1/fX (65 ms) Resolution 23 x 1/fX (1 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Minimum Interval Width 23 x 1/fX (1 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Table 7-4: 8-Bit Timer/Event Counter 51 Square-Wave Output Ranges Maximum Interval Width 212 x 1/fX (512 s) 214 x 1/fX (2 s) 215 x 1/fX (4 s) 216 x 1/fX (8 ms) 218 x 1/fX (32 ms) 220 x 1/fX (131 ms) Resolution 1/fX (2 s) 21 x 1/fX (8 s) 23 x 1/fX (16 s) 25 x 1/fX (32 s) 27 x 1/fX (128 s) 212 x 1/fX (512 s) Minimum Interval Width 24 x 1/fX (2 s) 26 x 1/fX (8 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 210 x 1/fX (128 s) 212 x 1/fX (512 s) Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses when operated at fX = 8.0 MHz. (4) PWM output TM50 and TM51 can generate an 8-bit resolution PWM output. User's Manual U16504EE1V1UD00 127 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.1.2 16-bit operation modes (1) Interval timer Interrupts are generated at the present interval time. Table 7-5: 16-Bit Timer/Event Counter TM50/TM51 Interval Times Maximum Interval Width 2 19 Minimum Interval Width 23 x 1/fX (1 s) Resolution 2 x 1/fX (1 s) 3 x 1/fX (65.5 ms) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) 221 x 1/fX (262 ms) 223 x 1/fX (1.05 ms) 224 x 1/fX (2.15 ms) 225 x 1/fX (4.25 s) 227 x 1/fX (16.7 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 7-6: 16-Bit Timer/Event Counter TM50/TM51 Square-Wave Output Ranges Maximum Interval Width 219 x 1/fX (65.5 ms) 221 x 1/fX (262 ms) 223 x 1/fX (1.05 ms) 224 x 1/fX (2.15 ms) 225 x 1/fX (4.25 s) 227 x 1/fX (16.7 s) Resolution 23 x 1/fX (1 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Minimum Interval Width 23 x 1/fX (1 s) 25 xx 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses when operated at fX = 8.0 MHz. 128 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.2 8-Bit Timer/Event Counters 50 and 51 Configurations The 8-bit timer/event counters 50 and 51 consist of the following hardware. Table 7-7: Item Timer register Register Timer output 8-Bit Timer/Event Counters 50 and 51 Configurations Configuration 8 bits x 2 (TM50, TM51) Compare register 8 bits x 2 (CR50, CR51) 2 (TO50, TO51) Timer clock select register 50 and 51 (TCL50, TCL51) Control register 8-bit timer mode control registers 50 and 51 (TMC50, TMC51) Port mode registers 3 and 9 (PM3, PM9) Figure 7-1: 8-Bit Timer/Event Counter 50 Block Diagram Internal Bus Mask Circuit 8-Bit Compare Register 50 (CR50) Selector INTTM50 TI50/P34/S27 fX/23 fX/25 fX/27 fX/28 fX/29 fX/211 Match Selector 8-Bit Counter 50 OVF (TM50) SQ INV R Selector TIO50/P34/S27 Clear S 3 Selector Level Inversion R TCL502 TCL501 TCL500 Timer Clock Select Register 50 (TCL50) TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 Timer Mode Control Register 50 (TMC50) Internal Bus Note: Refer to Figure 7-2 for details of configurations of 8-bit timer/event counters 50 and 51 output control circuits. User's Manual U16504EE1V1UD00 129 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Figure 7-2: 8-Bit Timer/Event Counter 51 Block Diagram Internal Bus Mask Circuit 8-Bit Compare Register 51 (CR51) Selector INTTM51 TI51/P91/S22 fX/24 fX/26 fX/27 fX/28 fX/210 fX/212 Match Selector 8-Bit Counter 51 OVF (TM51) SQ INV R Selector TIO51/P91/S22 Clear S 3 Selector Level Inversion R TCL512 TCL511 TCL510 Timer Clock Select Register 51 (TCL51) TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 Timer Mode Control Register 51 (TMC51) Internal Bus Note: Refer to Figure 7-3 for details of configurations of 8-bit timer/event counters 50 and 51 output control circuits. Figure 7-3: Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Output Control Circuit TMCn1 TMCn6 RESET Q S INV P34, P91 Output Latch PWM Output Circuit Timer Output F/F2 R Q S Level F/F Selector LVRn LVSn TMCn1 TMCn6 INTTMn TCEn INTTMn OVFn R TO50/P34/S27/TI50, TO51/P91/S22/TI51 PM34, PM91 TOEn Remarks: 1. The section in the broken line is an output control circuit. 2. n = 50, 51 130 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 (1) Compare register 50 and 51 (CR50, 51) These 8-bit registers compare the value set to CR50 to 8-bit timer register 5 (TM50) count value, and the value set to CR51 to the 8-bit timer register 51 (TM51) count value, and, if they match, generate interrupts request (INTTM50 and INTTM51, respectively). CR50 and CR51 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit memory manipulation instruction. The 00H to FFH values can be set. RESET input sets CR50 and CR51 values to 00H. Cautions: 1. To use PWM mode, set CRn value before setting TMCn (n = 50, 51) to PWM mode. 2. If the data is set in cascade mode, always set it after stopping the timer. (2) 8-bit timer registers 50 and 51 (TM50, TM51) These 8-bit registers count pulses. TM50 and TM51 are read with an 8-bit memory manipulation instruction. RESET input sets TM50 and TM51 to 00H. Caution: The cascade connection time becomes 00H even when the bit TCE50 of the timer TM50 is cleared. User's Manual U16504EE1V1UD00 131 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.3 8-Bit Timer/Event Counters 50 and 51 Control Registers The following three types of registers are used to control the 8-bit timer/event counters 50 and 51. * Timer clock select register 50 and 51 (TCL50, TCL51) * 8-bit timer mode control registers 50 and 51 (TMC50, TMC51) * Port mode register 0 (PM3, PM9) (1) Timer clock select register 50 (TCL50) This register sets count clocks of 8-bit timer register 50. TCL50 is set with an 8-bit memory manipulation instruction. RESET input sets TCL50 to 00H. Figure 7-4: Timer Clock Select Register 50 Format 7 TCL50 0 6 0 5 0 4 0 3 0 2 1 0 R/W Address FF71H After Reset 00H TCL502 TCL501 TCL500 R/W TCL502 0 0 0 0 1 1 1 1 TCL501 0 0 1 1 0 0 1 1 TCL500 0 1 0 1 0 1 0 1 8-bit Timer Register 50 Count Clock Selection TI50 falling edge Note TI50 rising edge Note fX/23 (1.0 MHz) fX/25 (250 KHz) fX/27 (62.5 KHz) fX/28 (31.25 KHz) fX/29 (15.6 KHz) fX/211 (3.9 KHz) Setting prohibited Other than above Note: When clock is input from the external, timer output (PWM output) cannot be used. Cautions: 1. When rewriting TCL50 to other data, stop the timer operation beforehand. 2. Set always bits 3 to 7 to "0". Remarks: 1. fX: Main system clock oscillation frequency 2. TI50: 8-bit timer register 50 input pin 3. Values in parentheses apply to operation with fX = 8.0 MHz 132 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 (2) Timer clock select register 51 (TCL51) This register sets count clocks of 8-bit timer register 51. TCL51 is set with an 8-bit memory manipulation instruction. RESET input sets TCL51 to 00H. Figure 7-5: Timer Clock Select Register 51 Format 7 TCL51 0 6 0 5 0 4 0 3 0 2 1 0 R/W Address FF75H After Reset 00H TCL512 TCL511 TCL510 R/W TCL512 0 0 0 0 1 1 1 1 TCL511 0 0 1 1 0 0 1 1 TCL510 0 1 0 1 0 1 0 1 8-bit Timer Register 51 Count Clock Selection TI51 falling edge Note TI51 rising edge Note fX/24 (500 KHz) fX/26 (125 KHz) fX/27 (62.5 KHz) fX/28 (31.25 KHz) fX/210 (7.8 KHz) fX/212 (1.9 KHz) Setting prohibited Other than above Note: When clock is input from the external, timer output (PWM output) cannot be used. Cautions: 1. When rewriting TCL51 to other data, stop the timer operation beforehand. 2. Set always bits 3 to 7 to "0". Remarks: 1. fX: Main system clock oscillation frequency 2. TI51: 8-bit timer register 51 input pin 3. Values in parentheses apply to operation with fX = 8.0 MHz User's Manual U16504EE1V1UD00 133 Chapter 7 8-Bit Timer/Event Counters 50 and 51 (3) 8-bit timer mode control register 50 (TMC50) This register enables/stops operation of 8-bit timer register 50, sets the operating mode of 8-bit timer register 50 and controls operation of 8-bit timer/event counter 50 output control circuit. It selects the R-S flip-flop (timer output F/F 1, 2) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 5 timer output enabling/disabling. TMC50 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC50 to 00H. Figure 7-6: 8-Bit Timer Mode Control Register 50 Format <7> 6 5 0 4 0 <3> LVS50 <2> LVR50 1 <0> R/W Address R/W FF70H After Reset 00H TMC50 TCE50 TMC506 TMC501 TOE50 TOE50 0 1 8-Bit Timer/Event Counter 50 Output Control Output disabled (Port mode) Output enabled In PWM Mode Active level selection Active high Active low In Other Mode Timer output F/F1 control Inversion operation disabled Inversion operation enabled 8-Bit Timer/Event Counter 50 Timer Output F/F1 Status Setting No change Timer output F/F1 reset (0) Timer output F/F1 set (1) Setting prohibited TMC501 0 1 LVS50 0 0 1 1 TMC506 0 1 TCE50 0 1 LVR50 0 1 0 1 8-Bit Timer/Event Counter 50 Operating Mode Selection Clear & start mode on match of TM50 and CR50 PWM mode (free-running) 8-Bit Timer Register 50 Operation Control Operation Stop (TM50 clear to 0) Operation Enable Cautions: 1. Timer operation must be stopped before setting TMC50. 2. If LVS50 and LVR50 are read after data are set, they will be 0. 3. Be sure to set bit 4 and bit 5 to 0. 134 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 (4) 8-bit timer mode control register 51 (TMC51) This register enables/stops operation of 8-bit timer register 51, sets the operating mode of 8-bit timer register 51 and controls operation of 8-bit timer/event counter 51 output control circuit. It selects the R-S flip-flop (timer output F/F 1, 2) setting/resetting, active level in PWM mode, inversion enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 51 timer output enabling/disabling. TMC51 is set with an 1-bit or an 8-bit memory manipulation instruction. RESET input sets TMC51 to 00H. Figure 7-7: 8-Bit Timer Mode Control Register 51 Format (1/2) <7> 6 5 0 4 TMC514 <3> LVS51 <2> LVR51 1 <0> R/W Address R/W FF74H After Reset 00H TMC51 TCE51 TMC516 TMC511 TOE51 TOE51 0 1 8-Bit Timer/Event Counter 51 Output Control Output disabled (Port mode) Output enabled TMC511 0 1 In PWM Mode Active level selection Active high Active low In Other Mode Timer output F/F1 control Inversion operation disabled Inversion operation enabled LVS51 0 0 1 1 LVR50 0 1 0 1 8-Bit Timer/Event Counter 51 Timer Output F/F1 Status Setting No change Timer output F/F1 reset (0) Timer output F/F1 set (1) Setting prohibited TMC514 0 1 Individual of cascade mode connection Individual mode (8-bit timer/counter mode) Cascade connection mode (16-bit timer/counter mode) User's Manual U16504EE1V1UD00 135 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Figure 7-7: 8-Bit Timer Mode Control Register 51 Format (2/2) TMC516 0 1 8-Bit Timer/Event Counter 51 Operating Mode Selection Clear & start mode on match of TM51 and CR51 PWM mode (free-running) TCE51 0 1 8-Bit Timer Register 51 Operation Control Operation Stop (TM51 clear to 0) Operation Enable Cautions: 1. Timer operation must be stopped before setting TMC51. 2. If LVS51 and LVR51 are read after data are set, they will be 0. 3. Be sure to set bit 5 to 0. (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P34/TI50/TO50/S27 pin for timer output, set PM34 and the output latch of P34 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 7-8: Port Mode Register 3 Format 7 PM3 PM37 6 PM36 5 PM35 4 PM34 3 1 2 1 1 1 0 1 R/W Address R/W FF23H After Reset FFH PM3n 0 1 PM3n Input/Output mode Selection (n = 4 to 7) Output mode (output buffer ON) Input mode (output buffer OFF) 136 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 (6) Port mode register 9 (PM9) This register sets port 9 input/output in 1-bit units. When using the P91/TI51/TO51/S22 pin for timer output, set PM91 and the output latch of P91 to 0. PM9 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM9 to FFH. Figure 7-9: Port Mode Register 9 Format 7 PM9 PM97 6 PM96 5 PM95 4 PM94 3 PM93 2 PM92 1 PM91 0 PM90 R/W Address R/W FF29H After Reset FFH PM9n 0 1 PM9n Input/Output mode Selection (n = 0 to 7) Output mode (output buffer ON) Input mode (output buffer OFF) User's Manual U16504EE1V1UD00 137 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.4 8-Bit Timer/Event Counters 50 and 51 Operations 7.4.1 Interval timer operations Setting the 8-bit timer mode control registers (TMC50 and TMC51) as shown in Figure 8-9 allows operation as an interval timer. Interrupts are generated repeatedly using the count value preset in 8-bit compare registers (CR50 and CR51) as the interval. When the count value of the 8-bit timer register 50 or 51 (TM50, TM51) matches the value set to CR50 or CR51, counting continues with the TM50 or TM51 value cleared to 0 and the interrupt request signal (INTTM50, INTTM51) is generated. Count clock of the 8-bit timer register 50 (TM50) can be selected with the timer clock select register 50 (TCL50) and count clock of the 8 bit timer register 51 (TM51) can be selected with the timer clock select register 51 (TCL51). Figure 7-10: 8-Bit Timer Mode Control Register Settings for Interval Timer Operation TMCn4 LVSn LVRn TMCn1 TOEn 0 0 0/1 0/1 0/1 0/1 TCEn TMCn6 TMCn 1 0 TM5n cascadation mode Clear and start on match of TMn and CRn TMn operation enable Setting Method (1) Set each register TCL5n : Selects the count clock CR5n : Compare value TMC5n : Selects the clear and start mode when TM5n and CR5n match. (TMC5n = 0000xxxx0B, x is not done care). When TCE5n = 1 is set, counting starts. When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). Then, INTTM5n is repeatedly generated during the same interval. When counting stops, set TCE5n = 0. (2) (3) (4) Remarks: 1. 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. 2. n = 50, 51 3. TMC5n4 is only available at TM51. 138 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Figure 7-11: Interval Timer Operation Timings (1/3) (a) When N = 00H to FFH t Count Clock TMn Count Value 00 01 N 00 01 N 00 Clear 01 N Clear CRn N N N N TCEn Count Start INTTMn Interrupt Acknowledge TOn Interval Time Interval Time Interval Time Interrupt Acknowledge Remarks: 1. Interval time = (N + 1) x t: N = 00H to FFH 2. n = 50, 51 (b) When CRn = 00H t Count clock TMn 00H CRn TCEn INTTMn TIOn 00H 00H 00H 00H Interval time Remark: n = 50, 51 User's Manual U16504EE1V1UD00 139 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Figure 7-11: Interval Timer Operation Timings (2/3) (c) When CRn = FFH t Count clock TMn CRn TCEn INTTMn Interrupt received TIOn Interval time Interrupt received FF 01 FE FF FF 00 FE FF FF 00 Remark: n = 50, 51 (d) Operated by CR5n transition (M < N) Count clock TMn N 00H CRn TCEn INTTMn TIOn CRn transition TMn overflows since M < N N M N FFH 00H M M 00H Remark: n = 50, 51 140 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Figure 7-11: Interval Timer Operation Timings (3/3) (e) Operated by CR5n transition (M > N) Count clock TMn CRn TCEn INTTMn TIOn CRn transition N<1 N N 00H 01H N M M<1 M 00H 01H Remark: n = 50, 51 User's Manual U16504EE1V1UD00 141 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Table 7-8: TCLn2 0 0 0 0 1 1 1 1 TCLn1 0 0 1 1 0 0 1 1 TCLn0 0 1 0 1 0 1 0 1 8-Bit Timer/Event Counters 50 Interval Times Maximum Interval Time 28 x T/n input cycle 28 x T/n input cycle 211 x 1/fX (256 s) 213 x 1/fX (1 ms) 215 x 1/fX (4 ms) 216 x 1/fX (8 ms) 217 x 1/fX (16 ms) 219 x 1/fX (65 ms) Setting prohibited Resolution T/n input edge input cycle T/n input edge input cycle 23 x 1/fX (1 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Minimum Interval Time T/n input cycle T/n input cycle 23 x 1/fX (1 S) 25 x 1/fX ((4 S) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Other than above Table 7-9: TCLn2 0 0 0 0 1 1 1 1 TCLn1 0 0 1 1 0 0 1 1 TCLn0 0 1 0 1 0 1 0 1 8-Bit Timer/Event Counters 51 Interval Times Maximum Interval Time 28 x T/n input cycle 28 x T/n input cycle 212 x 1/fX (512 s) 214 x 1/fX (2 ms) 215 x 1/fX (4 ms) 216 x 1/fX (8 ms) 218 x 1/fX (32 ms) 220 x 1/fX (131 ms) Setting prohibited Resolution T/n input edge input cycle T/n input edge input cycle 24 x 1/fX (2 s) 26 x 1/fX (8 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 210 x 1/fX (128 s) 212 x 1/fX (512 s) Minimum Interval Time T/n input cycle T/n input cycle 24 x 1/fX (2 s) 26 x 1/fX (8 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 210 x 1/fX (128 s) 212 x 1/fX (512 s) Other than above Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 8.0 MHz. 142 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI50/P34/522/TO50 and TI51/521/522/TO51 pins with 8-bit timer registers 50 and 51 (TM50 and TM51). TM50 and TM51 are incremented each time the valid edge specified with timer clock select registers 50 and 51 (TCL50 and TCL51) is input. Either rising or falling edge can be selected. When the TM50 and TM51 counted values match the values of 8-bit compare registers (CR50 and CR51), TM50 and TM51 are cleared to 0 and the interrupt request signals (INTTM50 and INTTM51) are generated. Figure 7-12: 8-Bit Timer Mode Control Register Setting for External Event Counter Operation TMCn4 LVSn LVRn TMCn1 TOEn TCEn TMCn6 TMCn 1 0 0 0 x x x 0 TOn output disable Clear & start mode on match of TMn and CRn TMn operation enable Remarks: 1. n = 50, 51 2. x: don't care Figure 7-13: External Event Counter Operation Timings (with Rising Edge Specified) Count Clock TMn Count Value 00 01 02 13 04 05 N-1 N 00 01 02 03 CRn N TCEn INTTMn Remarks: 1. N = 00H to FFH 2. n = 50, 51 User's Manual U16504EE1V1UD00 143 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.4.3 Square-wave output A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (CR50 and CR51). The TO50/P34/527/TI50 or TO51/P91/522/TI51 pin output status is reversed at intervals of the count value preset to CR50 or CR51 by setting bit 1 (TMC501) and bit 0 (TOE50) of the 8-bit timer output control register 5 (TMC50), or bit 1 (TMC511) and bit 0 (TOE51) of the 8-bit timer mode control register 6 (TMC51) to 1. This enables a square wave of a selected frequency to be output. Figure 7-14: 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation TMCn4 LVSn LVRn TMCn1 TOEn TCEn TMCn6 TMCn 1 0 0 0 0/1 0/1 1 1 TOn output enable Inversion of output on match of TMn and CRn Specifies TO1 output F/F1 initial value TM5n cascadation enable Clear and start mode on match of TMn and CRn TMn operation enable Setting Method (1) Set the registers Set the port latch and port mode register to 0. TCL5n : Selects the count clock CR5n : Compare value TMC5n : Selects the clear and start mode when TM5n and CR5n match. LVS5n 1 0 LVR5n 0 1 Setting State of Timer Output flip-flop High level output Low level output Inversion of timer output flip-flop enabled Timer output enabled TOE5n = 1 (2) (3) (4) When TCE5n = 1 is set, the counter starts operating. When the values of TM5n and CR5n match, the timer output flip-flop inverts. Also, INTTM5n is generated and TM5n is cleared to 00H. Then, the timer output flip-flop is inverted for the same interval to output a square wave from TO5n. When TIO50/P34/S27 or TIO51/P91/S22 pin is used as the timer output, set port mode register (PM26 or PM27), and output latch to 0. Caution: Remarks: 1. n = 50, 51 2. TMC5n4 is only available at TM51. 144 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Figure 7-15: Square-wave Output Operation Timing Count clock TMn count value 00H 01H 02H N-1 N 00H 01H 02H N-1 N 00H Count start CRn N T0n Note Note: TOn output initial value can be set by bits 2 and 3 (LVRn, LVSn) of the 8-bit timer mode control register TCMn. Remark: n = 50, 51 Table 7-10: 8-Bit Timer/Event Counters 50 Square-Wave Output Ranges Maximum Pulse Time 211 x 1/fX (256 s) Resolution 23 x 1/fX (1 s) Minimum Pulse Time 23 x 1/fX (1 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) 213 x 1/fX (1 ms) 215 x 1/fX (4 ms) 216 x 1/fX (8 ms) 217 x 1/fX (16 ms) 219 x 1/fX (65 ms) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Table 7-11: 8-Bit Timer/Event Counters 51 Square-Wave Output Ranges Maximum Pulse Time 212 x 1/fX (512 s) 214 x 1/fX (2 ms) 215 x 1/fX (4 ms) 216 x 1/fX (8 ms) 218 x 1/fX (32 ms) 220 x 1/fX (131 ms) Resolution 24 x 1/fX (2 s) 26 x 1/fX (8 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 210 x 1/fX (128 s) 212 x 1/fX (512 s) Minimum Pulse Time 24 x 1/fX (2 s) 26 x 1/fX (8 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 210 x 1/fX (128 s) 212 x 1/fX (512 s) Remarks: 1. Main system clock oscillation frequency 2. Values in parentheses when operated at fX = 8.0 MHz. 3. n = 50, 51 User's Manual U16504EE1V1UD00 145 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.4.4 PWM output operations Setting the 8-bit timer mode control registers (TMC50 and TMC51) as shown in Figure 8-14 allows operation as PWM output. Pulses with the duty rate determined by the values preset in 8-bit compare registers (CR50 and CR51) output from the TO50/P34/527/TI50 or TO51/P91/522/TI51 pin. Select the active level of PWM pulse with bit 1 of the 8-bit timer mode control register 50 (TMC50) or bit 1 of the 8-bit timer mode control register 51 (TMC51). This PWM pulse has an 8-bit resolution. The pulse can be converted into an analog voltage by integrating it with an external low-pass filter (LPF). Count clock of the 8-bit timer register 50 (TM50) can be selected with the timer clock select register 50 (TCL50) and count clock of the 8-bit timer register 51 (TM51) can be selected with the timer clock select register 51 (TCL51). PWM output enable/disable can be selected with bit 0 (TOE50) of TMC50 or bit 0 (TOE51) of TMC51. Figure 7-16: 8-Bit Timer Control Register Settings for PWM Output Operation TMCn4 LVSn LVRn TMCn1 TOEn TCEn TMCn6 TMCn 1 1 0 0 x x 0/1 1 TOn output enable Sets active level 8-bit timer/event counter mode PWM mode TMn operation enable Setting Method (1) (2) (3) (4) (5) Set the port latch and port mode register to "0". Set the active level width in the 8-bit compare register n (CR5n). Select the count clock in the timer clock selection register n (TCL5n). Set the active level in bit 1 (TMC5n1) of TMC5n. If bit 7 (TCE5n) of TMC5n is set to "1", counting starts. When counting starts, set TCE5n to "0". Remarks: 1. n = 50, 51 2. x: don't care PWM Output Operation (1) (2) (3) (4) (5) When counting starts, the PWM output (output from TO5n) outputs the inactive level until an overflow occurs. When the overflow occurs, the active level specified in step (1) in the setting method is output. The active level is output until CR5n and the count of the 8-bit counter n (TM5n) match. The PWM output after CR5n and the count match is the inactive level until an overflow occurs again. Steps (2) and (3) repeat until counting stops. If counting is stopped by TCE5n = 0, the PWM output goes to the inactive level. Remarks: 1. n = 50, 51 2. TMC5n4 is only available at TM51. User's Manual U16504EE1V1UD00 146 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Figure 7-17: PWM Output Operation Timing (Active high setting) CRn Changing (M N) Count Clock TMn Count Value CRn 00 01 02 FF 00 01 02 N N+1 N+2 N+3 00 M N N TCEn INTTMn OVFn TOn Inactive Level Inactive Level Active Level Inactive Level Remark: n = 50, 51 Figure 7-18: PWM Output Operation Timings (CRn0 = 00H, active high setting) CRn Changing (M 00) Count Clock TMn Count Value CRn 00 01 02 FF 00 01 02 FF 00 01 02 00 M 00 00 TCEn INTTMn OVFn TOn Inactive Level Inactive Level Remark: n = 50, 51 User's Manual U16504EE1V1UD00 147 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Figure 7-19: PWM Output Operation Timings (CRn = FFH, active high setting) Count Clock TMn Count Value CRn 00 01 02 FF 00 01 02 FF 00 01 02 00 FF FF FF TCEn INTTMn OVFn TOn Inactive Level Inactive Level Active Level Inactive Level Active Level Remark: n = 50, 51 Figure 7-20: PWM Output Operation Timings (CRn changing, active high setting) CRn Changing (N M) Count Clock TMn Count Value CRn0 FF 00 N 01 02 N N+1 N N+2 FF 00 01 M 02 M M+1 M M+2 M+3 00 TCEn INTTMn OVFn TOn Active Level Inactive Level Active Level Inactive Level Remark: Caution: n = 50, 51 If CRn is changed during TMn operation, the value changed is not reflected until TMn overflows. 148 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.5 Operation as interval timer (16-bit operation) (1) Cascade (16-bit timer) mode (TM50 and TM51) The 16-bit resolution timer/counter mode is set by setting bit 4 (TMC514) of the 8-bit timer mode control register 51 (TMC51) to "1". In this mode, TM50 and TM51 operate as a 16-bit interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance to 8-bit compare registers 50 and 51 (CR50 and CR51). Figure 7-21: 8-Bit Timer Mode Control Register Settings for 16-Bit Interval Timer Operation LVS50 LVR50 TMC501 TOE50 TCE50 TMC506 TMC50 1 0 0 0 0/1 0/1 0/1 0/1 Clear and start on match of TM50/TM51 and CR50/CR51 TM50 operation enable TCE51 TMC516 TMC51 TMC514 LVS51 L VR51 TMC511 TOE51 1 0 0 1 0/1 0/1 0/1 0 16-bit timer/counter mode Clear and start on match of TM50/TM51 and CR50/CR51 TM51 operation enable Remark: 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. User's Manual U16504EE1V1UD00 149 Chapter 7 8-Bit Timer/Event Counters 50 and 51 * TMC50 and TMC51: Select the mode that clears and starts the timer on coincidence between TM50 and CR50 (TM51 and CR51). TM50 TMC50 = 0000xxxxB x: don't care TM51 TMC51 = 0001xxxxB x: don't care <2> By setting TCE51 to 1 for TMC51 first, and then setting TCE50 to 1 for TMC50, the count operation is started. <3> When the value of CR50 (low byte) and CR51 (high byte) matches with TM50 and TM51, the interrupt INTTM50 is generated (TM50 and TM51 are cleared to 00H). <4> After that, INTTM50 is repeatedly generated at the same interval. Cautions: 1. Be sure to set the compare registers (CR50 and CR51) after stopping the timer operation. 2. Even if the timers are connected in cascade, TM51 generates INTTM51 when the count value of TM51 coincides with the value of CR51. Be sure to mask TM51 to disable it from generating an interrupt. 3. Set TCE50 and TCE51 in the order of TM51, then TM50. 4. Counting can be started or stopped by setting or clearing only TCE50 of TM50 to 1 or 0. 150 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Figure 7-22 shows an example of timing in the 16-bit resolution cascade mode. Figure 7-22: 16-Bit Resolution Cascade Mode (with TM50 and TM51) Count clock TM50 00H 01H N N+1 FFH 00H FFH 00H FFH 00H 01H N 00H 01H A 00H TM51 00H 01H 02H M-1 M 00H B 00H CR50 N CR51 M TCE50 TCE51 INTTM50 Interval time TO50 Interrupt request Enables operation Counting starts generated Level inverted Counter cleared Operation stops User's Manual U16504EE1V1UD00 151 Chapter 7 8-Bit Timer/Event Counters 50 and 51 Table 7-12: TCL502 0 0 0 0 1 1 1 1 8-Bit Timer/Event Counters Interval Times (16-Bit Timer/Event Counter Mode) TCL500 0 1 0 1 0 1 0 1 Minimum Interval Time TI50 input cycle TI50 input cycle 23 x 1/fX (1 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Maximum Interval Time 216 x TIn input cycle 216 x TIn input cycle 219 x 1/fX (65.5 ms) 221 x 1/fX (262 ms) 223 x 1/fX (1.05 s) 224 x 1/fX (2.15 s) 225 x 1/fX (4.25 s) 227 x 1/fX (16.7 s) Resolution TIn input cycle TIn input cycle 23 x 1/fX (1 s) 25 x 1/fX (4 s) 27 x 1/fX (8 s) 28 x 1/fX (16 s) 29 x 1/fX (32 s) 211 x 1/fX (256 s) TCL501 0 0 1 1 0 0 1 1 Table 7-13: TCL502 0 0 1 1 1 1 TCL501 1 1 0 0 1 1 TCL500 0 1 0 1 0 1 8-Bit Timer/Event Counter Square-Wave Output Ranges (16-Bit Timer/Event Counter Mode) Minimum Pulse Width 23 x 1/fX (1 s) Maximum Pulse Width 219 x 1/fX (65,5 ms) Resolution 23 x 1/fX (1 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 28 x 1/fX (32 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) 221 x 1/fX (262 ms) 223 x 1/fX (1.05 s) 224 x 1/fX (2.15 s) 225 x 1/fX (4.25 s) 227 x 1/fX (16.7 s) 25 x 1/fX (4 s) 27 x 1/fX (8 s) 28 x 1/fX (16 s) 29 x 1/fX (32 s) 211 x 1/fX (256 s) Caution: The clock selection in the cascade mode (16-bit timer/event counter mode) is done by the register TCL50. Remarks: 1. fX: Main system clock oscillation frequency. 2. Values in parentheses when operated at fX = 8.0 MHz. 152 User's Manual U16504EE1V1UD00 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.6 Cautions on 8-Bit Timer/Event Counters 50 and 51 (1) Timer start errors An error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts. This is because 8-bit timer registers 50 and 51 are started asynchronously with the count pulse. Figure 7-23: Count Pulse 8-bit Timer Registers 50 and 51 Start Timings TMn Count Value 00H 01H 02H 03H 04H Timer Start Remark: n = 50, 51 (2) Compare registers 50 and 51 sets The 8-bit compare registers (CR50 and CR51) can be set to 00H. Thus, when an 8-bit compare register is used as an event counter, one-pulse count operation can be carried out. Figure 7-24: TIn Input External Event Counter Operation Timings CRn 00H TMn Count Value 00H 00H 00H 00H TOn Interrupt Request Flag Remark: n = 50, 51 User's Manual U16504EE1V1UD00 153 Chapter 7 8-Bit Timer/Event Counters 50 and 51 (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR50 and CR51) are changed are smaller than those of 8-bit timer registers (TM50 and TM51), TM50 and TM51 continue counting, overflow and then restarts counting from 0. Thus, if the value (M) after CR50 and CR51 change is smaller than that (N) before change it is necessary to restart the timer after changing CR50 and CR51. Figure 7-25: Timings after Compare Register Change during Timer Count Operation Count Pulse CRn N M TMn Count Value X-1 X FFFFH 0000H 0001H 0002H Remark: n = 50, 51 154 User's Manual U16504EE1V1UD00 Chapter 8 8.1 8-Bit Timer 52 Functions 8-Bit Timer 52 The 8-bit timer 52 (TM52) has the following function: * Interval timer (1) 8-bit interval timer Interrupts are generated at the preset time intervals. Table 8-1: Minimum Interval Width 23 x 1/fX (1 s) 24 x 1/fX (2 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) 8-Bit Timer 52 Interval Times Maximum Interval Width 211 x 1/fX (256 s) 212 x 1/fX (512 s) 213 x 1/fX (1 s) 215 x 1/fX (4 ms) 217 x 1/fX (16 ms) 219 x 1/fX (65.5 ms) Resolution 23 x 1/fX (1 s) 24 x 1/fX (2 s) 25 x 1/fX (4 s) 27 x 1/fX (16 s) 29 x 1/fX (64 s) 211 x 1/fX (256 s) Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses when operated at fX = 8.0 MHz. 8.2 8-Bit Timer 52 Configurations The 8-bit timer 52 consists of the following hardware. Table 8-2: Item Timer register Compare Register Timer output Control register 8 bit (TM52) 8 bit (CR52) none Timer clock select register 52 (TCL52) 8-bit timer mode control register 52 (TMC52) 8-Bit Timer 52 Configurations Configuration Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses when operated at fX = 8.0 MHz. User's Manual U16504EE1V1UD00 155 Chapter 8 8-Bit Timer 52 Figure 8-1: 8-Bit Timer/Event Counter 52 Block Diagram Internal Bus 8-Bit Compare Register (CR50) Selector fx/23 fx/24 fx/25 fx/27 fx/29 fx/211 Match INTTM52 8-Bit Timer Register n (TM52) Clear Output Control Circuit Note Meter C/D 4 TCL TCL TCL 522 521 520 Timer Clock Select Register 52 Internal Bus TCE 52 8-Bit Timer Mode Control Register 52 Note: The output signal of the timer TM52 can be used as clock input of the meter controller/driver. (1) Compare register 52 (CR52) This 8-bit register compares the value with the count value of the 8-bit timer register 52 (TM52). If they match, an interrupt request (INTTM52) is generated. CR52 is set with an 8-bit memory manipulation instruction. RESET input sets CR52 value to 00H. (2) 8-bit timer register 52 (TM52) This 8-bit register counts pulses. TM52 is read with an 8-bit memory manipulation instruction. RESET input sets TM52 to 00H. 156 User's Manual U16504EE1V1UD00 Chapter 8 8-Bit Timer 52 8.3 8-Bit Timer 52 Control Registers The following two types of registers are used to control the 8-bit timer 52. * Timer clock select register 52 (TCL52) * 8-bit timer mode control register 52 (TMC52) (1) Timer clock select register 52 (TCL52) This register sets the count clock of the 8-bit timer register 52. TCL52 is set with an 8-bit memory manipulation instruction. RESET input sets TCL52 to 00H. Figure 8-2: Timer Clock Select Register 52 Format 7 TCL52 0 6 0 5 0 4 0 3 0 2 1 0 R/W Address FF79H After Reset 00H TCL522 TCL521 TCL520 R/W TCL522 0 0 1 1 1 1 TCL521 1 1 0 0 1 1 TCL520 0 1 0 1 0 1 8-bit Timer Register 52 Count Clock Selection fX/23 (1.0 MHz) fX/24 (500 KHz) fX/25 (250 KHz) fX/27 (62.5 KHz) fX/29 (15.6 KHz) fX/211 (3.9 KHz) Setting prohibited Other than above Caution: When rewriting TCL52 to other data, stop the timer operation beforehand. Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses when operated at fX = 8.0 MHz. User's Manual U16504EE1V1UD00 157 Chapter 8 8-Bit Timer 52 (2) 8-bit timer mode control register 52 (TMC52) This register enables/stops the operation of the 8-bit timer register 52. TMC52 is set with an 1-bit or an 8-bit memory manipulation instruction. RESET input sets TMC52 to 04H. Figure 8-3: 8-Bit Timer Output Control Register Format <7> TMC52 TCE52 6 0 5 0 4 0 3 0 2 0 1 TMC521 0 0 R/W Address R/W FF78H After Reset 00H TMC521 0 1 Timer Output F/F1 Control Inversion operation disabled Inversion operation enabled TCE52 0 1 8-Bit Timer Register 50 Operation Control Operation Stop (TM50 clear to 0) Operation Enable Cautions: 1. Timer operation must be stopped before setting TMC52. 2. Be sure to set bit 0 to 0 and bit 2 to bit 6 to 0. Remark: In case the timer TM52 is used as clock input of the meter C/D. The bit TMC521 has to be set to 1. 158 User's Manual U16504EE1V1UD00 Chapter 8 8-Bit Timer 52 8.4 8-Bit Timer 52 Operations 8.4.1 Interval timer operations Setting the 8-bit timer mode control register (TMC52) as shown in Figure 8-4 allows operation as an interval timer. An interrupt is generated repeatedly using the count value preset in the 8-bit compare register (CR52) as the interval. When the count value of the 8-bit timer register 52 (TM52) matches the value set to CR52, counting continues with the TM52 value cleared to 0 and the interrupt request signal INTTM52 is generated. Count clock of the 8-bit timer register 52 (TM52) can be selected with the timer clock select register 52 (TCL52). Figure 8-4: 8-Bit Timer Mode Control Register Settings for Interval Timer Operation TCE52 TMC52 1 0 0 0 0 0 0 0 TM52 operation enable Figure 8-5: Interval Timer Operation Timings (1/3) (a) When N = 00H to FFH t Count Clock TM52 Count Value 00 01 N 00 01 N 00 Clear 01 N Clear CR52 N N N N TCE52 Count Start INTTM52 Interrupt Acknowledge Interrupt Acknowledge Interval Time Interval Time Interval Time Remark: Interval time = (N + 1) x t: N = 00H to FFH User's Manual U16504EE1V1UD00 159 Chapter 8 8-Bit Timer 52 Figure 8-5: Interval Timer Operation Timings (2/3) (b) When CR52 = 00H t Count clock TM52 00H CR52 TCE52 INTTM52 00H 00H 00H 00H Interval time (c) When CR52 = FFH t Count clock TM52 CR52 TCE52 INTTM52 Interrupt received Interval time Interrupt received FF 01 FE FF FF 00 FE FF FF 00 160 User's Manual U16504EE1V1UD00 Chapter 8 8-Bit Timer 52 Figure 8-5: Interval Timer Operation Timings (3/3) (d) Operated by CR52 transition (M < N) Count clock TM52 N 00H CR52 TCE52 INTTM52 N M N FFH 00H M M 00H CR52 transition TM52 overflows since M < N (e) Operated by CR52 transition (M > N) Count clock TM52 CR52 TCE52 INTTM52 N N 00H 01H N M 1 M 00H 01H CR52 transition User's Manual U16504EE1V1UD00 161 [MEMO] 162 User's Manual U16504EE1V1UD00 Chapter 9 9.1 Watch Timer Functions The watch timer has the following functions: * Watch timer * Interval timer Watch Timer The watch timer and the interval timer can be used simultaneously. The Figure 9-1 shows Watch Timer Block Diagram. Figure 9-1: Block Diagram of Watch Timer Clear Selector fX/2 7 Selector fW fW 24 9-bit prescaler fW 25 fW 26 fW 27 fW 28 fW 29 5-bit counter Clear INTWT f X /2 11 Selector INTWTI WTM7 WTM6 WTM5 WTM4 WTM3 Watch timer mode control register (WTM) Internal bus 0 WTM1 WTM0 User's Manual U16504EE1V1UD00 163 Chapter 9 (1) Watch timer Watch Timer When the main system clock or subsystem clock is used, interrupt requests (INTWT) are generated at 0.25 second intervals. (2) Interval timer Interrupt requests (INTWTI) are generated at the preset time interval. Table 9-1: Interval Time 24/fW 25/fW 26/fW 27/fW 28/fW 29/fW Interval Timer Interval Time When operated at fX = 8.00 MHz 256 s 512 s 1 ms 2 ms 4 ms 8.19 ms When operated at fX = 4.00 MHz 512 s 1 ms 2 ms 4 ms 8.19 ms 16.3 ms Remarks: 1. fX: Main system clock oscillation frequency 2. fW: Watch timer clock frequency 9.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 9-2: Item Counter Prescaler Control register Watch Timer Configuration Configuration 5 bits x 1 9 bits x 1 Watch timer mode control register (WTM) 164 User's Manual U16504EE1V1UD00 Chapter 9 Watch Timer 9.3 Watch Timer Mode Register (WTM) This register sets the watch timer count clock, the watch timer operating mode, and prescaler interval time and enables/disables prescaler and 5-bit counter operations. WTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WTM to 00H. Figure 9-2: Watch Timer Mode Control Register (WTM) Format (1/2) 7 WTM WTM7 6 WTM6 5 WTM5 4 WTM4 3 WTM3 2 0 1 WTM1 0 WTM0 R/W Address R/W FF41H After Reset 00H WTM7 0 1 Input clock set to fX / 27 Input clock set to fX / 211 Watch Timer Count Clock Selection Prescaler Interval Time Selection WTM6 WTM5 WTM4 fX = 8.00 MHz Operation fW =fX/27 24/fW (256 s) 25/fW (512 s) 26/fW (1 ms) 27/fW (2 ms) 28/fW (4 ms) 29/fW (8.19 ms) fX = 4.00 MHz Operation fW =fX/27 24/fW (512 s) 25/fWw (1 ms) 26/fW (2 ms) 27/fW (4 ms) 28/fW (8.19 ms) 29/fW (16.38 ms) 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 Setting prohibited WTM3 0 1 Watch Operating Mode Selections Normal operating mode (interrupt generation at 214/fW) Fast feed operating mode (interrupt generation at 25/fW) User's Manual U16504EE1V1UD00 165 Chapter 9 Figure 9-2: Watch Timer Watch Timer Mode Control Register (WTM) Format (2/2) WTM1 0 1 Clear after operation stop Operation enable 5-Bit Counter Operation Control WTM0 0 1 Clear after operation stop Operation enable Prescaler Operation Control Caution: When the watch timer is used, the prescaler should not be cleared frequently. When rewriting WTM4 to WTM6 to other data, stop the timer operation beforehand. Remarks: 1. fW: Watch timer clock frequency (fX/27 or fX/211) 2. fX: Main system clock oscillation frequency 166 User's Manual U16504EE1V1UD00 Chapter 9 Watch Timer 9.4 Watch Timer Operations 9.4.1 Watch timer operation When the 8.00-MHz main system clock is used, the timer operates as a watch timer and generates interrupt requests at a constant time interval. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer mode control register (WTM) are set to 1, the count operation starts. When set to 0, the 5-bit counter is cleared and the count operation stops. For simultaneous operation of the interval timer, zero-second start can be only the watch timer by setting WTM1 to 0. However, since the 9-bit prescaler is not cleared the first overflow of the watch timer (INTWT) after zero-second start may include an error of up to 29 x 1/fW. 9.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM). Table 9-3: WTM6 0 0 0 0 1 1 WTM5 0 0 1 1 0 0 Other than above WTM4 0 1 0 1 0 1 Interval Timer Operation fX = 8.00 MHz Operation fX = 4.00 MHz Operation 256 s 512 s 1 ms 2 ms 4 ms 8.19 ms Setting prohibited 512 s 1 ms 2 ms 4 ms 8.19 ms 16.3 ms Interval Time 24 x 1/fW 25 x 1/fW 26 x 1/fW 27 x 1/fW 28 x 1/fW 29 x 1/fW Remarks: 1. fX : Main system clock oscillation frequency 2. fW : Watch timer clock frequency User's Manual U16504EE1V1UD00 167 Chapter 9 Figure 9-3: Watch Timer Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Start Count clock fw Watch timer interrupt INTWT Interval timer interrupt INTWTI Interval timer (T) T Overflow Overflow Interrupt time of watch timer Interrupt time of watch timer Remark: fW : Watch timer clock frequency 168 User's Manual U16504EE1V1UD00 Chapter 10 Watchdog Timer 10.1 Watchdog Timer Functions The watchdog timer has the following functions: * Watchdog timer * Interval timer Caution: Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM). (1) Watchdog timer mode Upon detection of an inadvertent program loop, a non-maskable interrupt request or RESET can be generated. Table 10-1: Watchdog Timer Inadvertent Program Overrun Detection Times Runaway Detection Time 212 x 1/fX 212 x 1/fX (512 s) 213 x 1/fX (1 ms) 214 x 1/fX (2 ms) 215 x 1/fX (4 ms) 216 x 1/fX (8.19 ms) 217 x 1/fX (16.38 ms) 218 x 1/fX (32.76 ms) 220 x 1/fX (131 ms) 213 x 1/fX 214 x 1/fX 215 x 1/fX 216 x 1/fX 217 x 1/fX 218 x 1/fX 220 x 1/fX Remark: Figures in parentheses apply to operation with fX = 8.0 MHz. User's Manual U16504EE1V1UD00 169 Chapter 10 (2) Interval timer mode Watchdog Timer Interrupts are generated at the preset time intervals. Table 10-2: Interval Times Interval Time 212 x 1/fX 213 x 1/fX 214 x 1/fX 215 x 1/fX 216 x 1/fX 217 x 1/fX 218 x 1/fX 220 x 1/fX 212 x 1/fX (512 s) 213 x 1/fX (1 ms) 214 x 1/fX (2 ms) 215 x 1/fX (4 ms) 216 x 1/fX (8.19 ms) 217 x 1/fX (16.38 ms) 218 x 1/fX (32.76 ms) 220 x 1/fX (131 ms) Remark: Figures in parentheses apply to operation with fX = 8.0 MHz. 170 User's Manual U16504EE1V1UD00 Chapter 10 Watchdog Timer 10.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 10-3: Item Control register Watchdog Timer Configuration Configuration Timer clock select register (WDCS) Watchdog timer mode register (WDTM) Figure 10-1: Watchdog Timer Block Diagram Internal Bus fX /212 Prescaler WDTMK fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 211 Selector RUN WDTIF 8-Bit Counter Control Circuit INTWDT Maskable Interrupt Request RESET INTWDT Non-Maskable Interrupt Request 3 WDCS2 WDCS1 WDCS0 WDTM4 WDTM3 Watchdog Timer Clock Selection Register Internal Bus Watchdog Timer Mode Register User's Manual U16504EE1V1UD00 171 Chapter 10 Watchdog Timer 10.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. * Watchdog timer clock select register (WDCS) * Watchdog timer mode register (WDTM) (1) Watchdog timer clock select register (WDCS) This register sets the watchdog timer count clock. WDCS is set with 8-bit memory manipulation instruction. RESET input sets WDCS to 00H. Figure 10-2: Timer Clock Select Register 2 Format 7 WDCS 0 6 0 5 0 4 0 3 0 2 1 0 R/W Address FF42H After Reset 00H WDCS2 WDCS1 WDCS0 R/W WDCS2 0 0 0 0 1 1 1 1 WDCS1 0 0 1 1 0 0 1 1 WDCS0 0 1 0 1 0 1 0 1 Overflow Time of Watchdog Timer fX/212 (512 s) fX/213 (1 ms) fX/214 (2 ms) fX/215 (4 ms) fX/216 (8.19 ms) fX/217 (16.38 ms) fX/218 (32.76 ms) fX/220 (131 ms) Caution: When rewriting WDCS to other data, stop the timer operation beforehand. Remarks: 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.0 MHz. 172 User's Manual U16504EE1V1UD00 Chapter 10 (2) Watchdog timer mode register (WDTM) Watchdog Timer This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with an 1-bit or an 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 10-3: Watchdog Timer Mode Register Format <7> WDTM RUN 6 0 5 0 4 3 2 0 1 0 0 0 R/W Address R/W FFF9H After Reset 00H WDTM4 WDTM3 WDTM4 0 1 1 WDTM3 X 0 1 Watchdog Timer Operation Mode Selection Note 1 Interval timer mode (Maskable interrupt occurs upon generation of an overflow) Watchdog timer mode 1 (Non-maskable interrupt occurs upon generation of an overflow) Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow) RUN 0 1 Count stop Watchdog Timer Operation Mode Selection Note 2 Counter is cleared and counting starts Notes: 1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software. 2. Once set to 1, RUN cannot be cleared to 0 by software. Thus, once counting starts, it can only be stopped by RESET input. Caution: When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by watchdog timer clock select register. x = don't care. Remark: User's Manual U16504EE1V1UD00 173 Chapter 10 Watchdog Timer 10.4 Watchdog Timer Operations 10.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (WDCS0 to WDCS2) of the timer clock select register (WDCS). Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within the set overrun detection time interval. The watchdog timer can be cleared and counting is started by setting RUN to 1. If RUN is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable interrupt request is generated according to the WDTM bit 3 (WDTM3) value. The watchdog timer can be cleared when RUN is set to 1. The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction. Cautions: 1. The actual overrun detection time may be shorter than the set time by a maximum of 0.5%. 2. When the subsystem clock is selected for CPU clock, watchdog timer count operation is stopped. Table 10-4: WDCS2 0 0 0 0 1 1 1 1 WDCS1 0 0 1 1 0 0 1 1 Watchdog Timer Overrun Detection Time WDCS0 0 1 0 1 0 1 0 1 Runaway Detection Time fX/212 (512 s) fX/213 (1 ms) fX/214 (2 ms) fX/215 (4 ms) fX/216 (8.19 ms) fX/217 (16.38 ms) fX/218 (32.76 ms) fX/220 (131 ms) Remarks: 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.0 MHz. 174 User's Manual U16504EE1V1UD00 Chapter 10 10.4.2 Interval timer operation Watchdog Timer The watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 (WDTM3) of the watchdog timer mode register (WDTM) is set to 0, respectively. When the watchdog timer operates as interval timer, the interrupt mask flag (TMMK4) and priority specify flag (TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupts, the INTWDT default has the highest priority. The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set bit 7 (RUN) of WDTM to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction. Cautions: 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless RESET input is applied. 2. The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0.5%. 3. When the subsystem clock is selected for CPU clock, watchdog timer count operation is stopped. Table 10-5: WDCS2 0 0 0 0 1 1 1 1 WDCS1 0 0 1 1 0 0 1 1 Interval Timer Interval Time WDCS0 0 1 0 1 0 1 0 1 Interval Time fX/212 (512 s) fX/213 (1 ms) fX/214 (2 ms) fX/215 (4 ms) fX/216 (8.19 ms) fX/217 (16.38 ms) fX/218 (32.76 ms) fX/220 (131 ms) Remarks: 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.0 MHz. User's Manual U16504EE1V1UD00 175 [MEMO] 176 User's Manual U16504EE1V1UD00 Chapter 11 Clock Output Control Circuit 11.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the clock output selection register (CKS) are output from the PCL/P61/SGOA pin. Follow the procedure below to route clock pulses to the SGOA pin: (1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (CCS0 to CCS2) of CKS. (2) Set the P61 output latch to 0. (3) Set bit 1 (PM61) of port mode register 6 to 0 (set to output mode). (4) Set bit 4 (CLOE) of clock output selection register to 1. Caution: Remark: Clock output cannot be used when setting P61 output latch to 1. When clock output enable/disable is switched, the clock output control circuit does not generate pulses with smaller widths than the original signal carries. (See the portions marked with * in Figure 10-1). Figure 11-1: CLOE Remote Controlled Output Application Example PCL/P61/SGOA Pin Output * * User's Manual U16504EE1V1UD00 177 Chapter 11 Clock Output Control Circuit 11.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 11-1: Item Clock Output Control Circuit Configuration Configuration Clock output selection register (CKS) Port mode register 6 (PM6) Control register Figure 11-2: Clock Output Control Circuit Block Diagram fX fX/2 fX/23 fX/24 fX/2 fX/2 5 6 Selector fX/22 Synchronizing Circuit PCL /P61/SGOA fX/27 4 CLOE CCS2 CCS1 CCS0 Clock Output Selection Register P61 Output Latch PM61 Port Mode Register 6 Internal Bus 178 User's Manual U16504EE1V1UD00 Chapter 11 Clock Output Control Circuit 11.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. * Clock output selection register (CKS) * Port mode register 6 (PM6) (1) Clock output selection register (CKS) This register sets PCL output clock. CKS is set with an 1-bit or an 8-bit memory manipulation instruction. RESET input sets CKS to 00H. Caution: When enabling PCL output, set CCS0 to CCS2, then set 1 in CLOE with an 1-bit memory manipulation instruction. Figure 11-3: Timer Clock Select Register 0 Format 7 CKS 0 6 0 5 0 <4> CLOE 3 0 2 CCS2 1 CCS1 0 CCS0 R/W Address R/W FF40H After Reset 00H CCS2 0 0 0 0 1 1 1 1 CCS1 0 0 1 1 0 0 1 1 CCS0 0 1 0 1 0 1 0 1 PCL Output Clock Selection fX (8 MHz) fX/21 (4 MHz) fX/22 (2 MHz) fX/23 (1 MHz) fX/24 (500 KHz) fX/25 (250 KHz) fX/26 (125 KHz) fX/27 (62.5 KHz) Setting prohibited Other than above CLOE 0 1 Output disable Output enable PCL Output Control Remarks: 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.0 MHz. User's Manual U16504EE1V1UD00 179 Chapter 11 (2) Port mode register 6 (PM6) Clock Output Control Circuit With this register the port mode PM3 can be set bit-wise. When using the P61/PCL/SGOA pin for clock output function, set PM61 and output latch of P61 to 0. PM6 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM6 to FFH. Figure 11-4: Port Mode Register 6 Format 7 PM6 0 6 0 5 PM65 4 PM64 3 PM63 2 PM62 1 PM61 0 PM60 R/W Address R/W FF26H After Reset FFH PM6n 0 1 PM6n Pin Input/Output Mode Selection (n = 0 to 5) Output mode (output buffer ON) Input mode (output buffer OFF) 180 User's Manual U16504EE1V1UD00 Chapter 12 A/D Converter 12.1 A/D Converter Functions The A/D converter is an 8-bit resolution converter that converts analog input voltages into digital values. It can control up to 5 analog input channels (ANI0 to ANI4). This A/D converter has the following functions: (1) A/D conversion with 8-bit resolution With the analog input channel specification register (ADS1) one out of 5 analog input channels is selected. Conversion time and start of sampling is controlled by the A/D converter mode register (ADM). Each time the conversion has been completed, an interrupt request (INTAD) is generated. (2) Power-fail detection function The result of an A/D conversion (value of the ADCR1 register) and the value of PFT register (PFT: power-fail compare threshold value register) are compared. If the condition for comparison is satisfied, the INTAD is generated. Figure 12-1: A/D Converter Block Diagram ANI0/P10 Sample & hold circuit Voltage comparator Selector Tap selector AVDD/AVREF ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 Successive approximation register (SAR) AVss Control circuit INTAD 3 A/D conversion result register (ADCR1) ADS12 ADS11ADS10 ADCS1 FR12 FR11 FR10 A/D converter mode register Analog input channel specification register Internal bus User's Manual U16504EE1V1UD00 181 Chapter 12 Figure 12-2: A/D Converter Power-Fail Detection Function Block Diagram PFCM PFEN ANI0/P10 ANI2/P12 ANI3/P13 ANI4/P14 Multiplexer ANI1/P11 Selector INTAD A/D converter Comparator PFEN PFCM Power-fail compare mode register (PFM) Internal bus Power-fail compare threshold value register (PFT) 12.2 A/D Converter Configuration A/D converter consists of the following hardware. Table 12-1: Item Analog input Registers A/D Converter Configuration Configuration 5 channels (ANI0 to ANI4) Successive approximation register (SAR) A/D conversion result register (ADCR1) A/D converter mode register (ADM1) Control registers Analog input channel specification register (ADS1) Power-fail compare mode register (PFM) Power-fail compare threshold value register (PFT) (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is set (end of A/D conversion), the SAR contents are transferred to the A/D conversion result register. 182 User's Manual U16504EE1V1UD00 Chapter 12 (2) A/D conversion result register (ADCR1) A/D Converter This register holds the A/D conversion result. Each time when the A/D conversion ends, the conversion result is loaded from the successive approximation register. ADCR1 is read with an 8-bit memory manipulation instruction. RESET input clears ADCR1 to 00H. Caution: If a write operation is executed to the A/D converter mode register (ADM1) and the analog input channel specification register (ADS1), the contents of ADCR1 are undefined. Read the conversion result before a write operation is executed to ADM1 and ADS1. If a timing other than the above is used, the correct conversion result may not be read. (3) Sample & hold circuit The sample & hold circuit samples each analog input sequential applied from the input circuit, and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage. (5) Series resistor string The series resistor string is in AVDD to AVSS, and generates a voltage to be compared to the analog input. (6) ANI0 to ANI4 pins These are five analog input pins to feed analog signals to the A/D converter. ANI0 to ANI4 are alternate-function pins that can also be used for digital input. Caution: Use ANI0 to ANI4 input voltages within the specified range. If a voltage higher than AVDD or lower than AVSS is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (7) AVDD pin (shared with AVREF pin) This pin supplies the A/D converter reference voltage and is used as the power supply pin of the A/ D-converter. It converts signals from ANI0 to ANI4 into digital signals according to the voltage applied between AVDD and AVSS. Keep the AVDD/AVREF pin always at the same potential as the VDD pin, even when the A/D-converter is not used. (8) AVSS pin This is the GND potential pin of the A/D converter. Always keep it at the same potential as the VSS pin even when not using the A/D converter. User's Manual U16504EE1V1UD00 183 Chapter 12 A/D Converter 12.3 A/D Converter Control Registers The following 4 types of registers are used to control A/D converter. * A/D converter mode register (ADM1) * Analog input channel specification register (ADS1) * Power-fail compare mode register (PFM) * Power-fail compare threshold value register (PFT) (1) A/D converter mode register (ADM1) This register sets the conversion time for analog input to be A/D converted, conversion start/stop, and external trigger. ADM1 is set with an 1-bit or an 8-bit memory manipulation instruction. RESET input clears ADM1 to 00H. Figure 12-3: A/D Converter Mode Register (ADM1) Format <7> ADM1 ADCS1 6 0 5 FR12 4 FR11 3 FR10 2 0 1 0 0 0 R/W Address R/W FF98H After Reset 00H ADCS1 0 1 A/D Conversion Operation Control Stop conversion operation Enable conversion operation FR12 0 0 0 1 1 1 FR11 0 0 1 0 0 1 FR10 0 1 0 0 1 0 Conversion Time Selection Note 144/fX 120/fX 96/fX 288/fX 240/fX 192/fX Setting prohibited Other than above Note: Set so that the A/D conversion time is 14 s or more. Caution: Remark: Bits 0 to 2 and bit 6 must be set to 0. fX: Main system clock oscillation frequency. 184 User's Manual U16504EE1V1UD00 Chapter 12 (2) A/D Converter Analog input channel specification register (ADS1) This register specifies the analog voltage input port for A/D conversion. ADS1 is set with an 8-bit memory manipulation instruction. RESET input clears ADS1 to 00H. Figure 12-4: Analog Input Channel Specification Register (ADS1) Format 7 ADS1 0 6 0 5 0 4 0 3 0 2 ADS12 1 ADS11 0 ADS10 R/W Address R/W FF99H After Reset 00H ADS12 0 0 0 0 1 ADS11 0 0 1 1 0 ADS10 0 1 0 1 0 Analog Input Channel Specification ANI0 ANI1 ANI2 ANI3 ANI4 Setting prohibited Other than above Caution: Bits 3 to 7 must be set to 0. User's Manual U16504EE1V1UD00 185 Chapter 12 (3) Power-fail compare mode register (PFM) A/D Converter The power-fail compare mode register (PFM) controls a comparison operation. PFM is set with an 1-bit or an 8-bit memory manipulation instruction. RESET input clears PFM to 00H. Figure 12-5: Power-Fail Compare Mode Register (PFM) Format 7 PFM PFEN 6 PFCM 5 0 4 0 3 0 2 0 1 0 0 0 R/W Address R/W FF9AH After Reset 00H PFEN 0 1 Enables Power-Fail Comparison Disables power-fail comparison (used as normal A/D converter) Enables power-fail comparison (used to detect power failure) PFCM 0 ADCR1 PFT ADCR1 < PFT ADCR1 PFT ADCR1 < PFT Power-Fail Compare Mode Selection Generates interrupt request signal INTAD Does not generate interrupt request signal INTAD Does not generate interrupt request signal INTAD Generates interrupt request signal INTAD 1 Caution: Bits 0 to 5 must be set to 0. (4) Power-fail compare threshold value register (PFT) The power-fail compare threshold value register (PFT) sets a threshold value against which the result of A/D conversion is to be compared. PFT is set with an 8-bit memory manipulation instruction. RESET input clears PFT to 00H. Figure 12-6: Power-fail compare threshold value register (PFT) 7 PFT PFT7 6 PFT6 5 PFT5 4 PFT4 3 PFT3 2 PFT2 1 PFT1 0 PFT0 R/W Address R/W FF9BH After Reset 00H 186 User's Manual U16504EE1V1UD00 Chapter 12 A/D Converter 12.4 A/D Converter Operations 12.4.1 Basic Operations of A/D Converter <1> Select one channel for the A/D conversion with the analog input channel specification register (ADS1). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the analog input voltage is held until the A/D conversion operation is complete. <4> Upon completion of the comparison of 8-bits, the digital result of the A/D conversion resides in SAR. The result is latched in the A/D conversion result register (ADCR1). At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. Caution: The first A/D conversion value just after starting the A/D conversion (ADCS1=1) is undefined. Figure 12-7: Basic Operation of 8-Bit A/D Converter Conv rsion time e Sampling time A/D converter operation Sampling A/D conv rsion e SAR Undefined 80H C0H or 40H Conversion result ADCR1 Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS1) of the A/D converter mode register (ADM1) is reset (to 0) by software. If a write operation to the ADM1 and analog input channel specification register (ADS1) is performed during an A/D conversion operation, the conversion operation is initialized, and if the ADCS1 bit is set (to 1), conversion starts again from the beginning. RESET input sets the A/D conversion result register (ADCR1) to 00H. User's Manual U16504EE1V1UD00 187 Chapter 12 12.4.2 Input voltage and conversion results A/D Converter The relation between the analog input voltage input to the analog input pins (ANI0 to ANI4) and the A/D conversion result (stored in the A/D conversion result register (ADCR1)) is given by the following expression. ADCR1 = INT ( VIN AVDD x 256 + 0.5) or (ADCR1 - 0.5) x AVDD 256 - VIN < (ADCR1 + 0.5) x AVDD 256 where, INT( ) VIN AVDD : Function which returns integer part of value in parentheses : Analog input voltage : AVDD pin voltage ADCR1 : A/D conversion result register (ADCR1) value Figure 12-8, "Relation between Analog Input Voltage and A/D Conversion Result," on page 189 shows the relation between the analog input voltage and the A/D conversion result. 188 User's Manual U16504EE1V1UD00 Chapter 12 Figure 12-8: A/D Converter Relation between Analog Input Voltage and A/D Conversion Result 255 254 253 A/D conversion result (ADCR1) 3 2 1 0 1 3 2 5 3 1 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 1 Input voltage/AVDD User's Manual U16504EE1V1UD00 189 Chapter 12 12.4.3 A/D converter operation mode A/D Converter The operation mode of the A/D converter is the select mode. One analog input channel is selected from among ANI0 to ANI4 with the analog input channel specification register (ADS1) and A/D conversion is performed when bit ADCS1 in ADM1 is set to 1. The following two types of functions can be selected by setting the PFEN flag of the PFM register. * Normal 8-bit A/D converter (PFEN = 0) * Power-fail detection function (PFEN = 1) (1) A/D conversion (when PFEN = 0) When bit 7 (ADCS1) of the A/D converter mode register (ADM1) is set to 1 and bit 7 of the powerfail compare mode register (PFM) is set to 0, A/D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ADS1) starts. Upon the end of the A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR1), and the interrupt request signal (INTAD) is generated. After one A/D conversion operation has ended, the next conversion operation is immediately started. A/D conversion operations are repeated until new data is written to ADS1. If ADS1 is rewritten during A/D conversion operation, the A/D conversion operation under execution is stopped, and A/D conversion of a newly selected analog input channel is started. If data with ADCS1 set to 0 is written to ADM1 during A/D conversion operation, the A/D conversion operation stops immediately. (2) Power-fail detection function (when PFEN = 1) When bit 7 (ADCS1) of the A/D converter mode register (ADM1) and bit 7 (PFEN) of the power-fail compare mode register (PFM) are set to 1, A/D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ADS1) starts. Upon the end of the A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR1), compared with the value of the power-fail compare threshold value register (PFT), and INTAD is generated under the condition specified by the PFCM flag of the PFM register. Caution: When executing power-fail comparison, the interrupt request signal (INTAD) is not generated on completion of the first conversion after ADCS1 has been set to 1. INTAD is valid from completion of the second conversion. 190 User's Manual U16504EE1V1UD00 Chapter 12 Figure 12-9: ADM1 rewrite ADCS1 = 1 A/D Converter A/D Conversion ADS1 rewrite ADCS1 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion suspended; Conversion results are not stored Stop ADCR1 ANIn ANIn ANIm INTAD (PFEN = 0) INTAD (PFEN = 1) First conversion Condition satisfied Remarks: 1. n = 0, 1, ..., 4 2. m = 0, 1, ..., 4 User's Manual U16504EE1V1UD00 191 Chapter 12 A/D Converter 12.5 A/D Converter Precautions (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced ( 250 A @ AVDD = 5 V) by setting bit 7 (ADCS1) of the A/D converter mode register (ADM1) to 0 in order to stop conversion. Figure 11-10 shows how to reduce the current consumption in the standby mode. Figure 12-10: Example Method of Reducing Current Consumption in Standby Mode AV DD AV REF AD-Converter power supply AV DD P-ch ADCS1 Series resistor string ( ~ 21 K9) AVSS (2) Input range of ANI0 to ANI4 The input voltages of ANI0 to ANI4 should be within the specification range. In particular, if a voltage higher than AVDD or lower than AVSS is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) Contending operations (a) Contention between A/D conversion result register (ADCR1) write and ADCR1 read by instruction upon the end of conversion ADCR1 read is given priority. After the read operation, the new conversion result is written to ADCR1. (b) Contention between ADCR1 write and A/D converter mode register (ADM1) write or analog input channel specification register (ADS1) write upon the end of conversion ADM1 or ADS1 write is given priority. ADCR1 write is not performed, nor is the conversion end interrupt request signal (INTAD) generated. 192 User's Manual U16504EE1V1UD00 Chapter 12 (4) Noise counter measures A/D Converter To maintain 8-bit resolution, attention must be paid to noise input to pin AVDD and pins ANI0 to ANI4. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 11-11 to reduce noise. Figure 12-11: Analog Input Pin Handling If there is a possibility that noise equal to or higher than AVDD or equal to or lower than AV SS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVDD /AV REF ANI0 to ANI4 C = 100 to 1000 pF AVSS VSS (5) ANI0 to ANI4 The analog input pins (ANI0 to ANI4) also function as input port pins (P10 to P14). When A/D conversion is performed with any of pins ANI0 to ANI4 selected, do not execute a port input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (6) AVDD/AVREF pin input impedance A series resistor string of approximately 21 k is connected between the AVDD/AVREF pin and the AVSS pin. Therefore, if the output impedance of the reference voltage is high, this will result in parallel connection to the series resistor string between the AVDD pin and the AVSS pin, and there will be a large reference voltage error. User's Manual U16504EE1V1UD00 193 Chapter 12 (7) Interrupt request flag (ADIF) A/D Converter The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS1) is changed. Caution is therefore required if a change of analog input pin is performed during A/D conversion. The A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS1 rewrite. If the ADIF is read immediately after the ADS1 rewrite, the ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended. When the A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 12-12: A/D Conversion End Interrupt Request Generation Timing ADS1 rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not ended. ADS1 rewrite (start of ANIn conversion) A/D conversion ANIn ANIn ANIm ANIm ADCR1 ANIn ANIn ANIm ANIm INTAD Remarks: 1. n = 0, 1, ..., 4 2. m = 0, 1, ..., 4 (8) Read of A/D conversion result register (ADCR1) When a write operation is executed to A/D converter mode register (ADM1) and analog input channel specification register (ADS1), the contents of ADCR1 are undefined. Read the conversion result before write operation is executed to ADM1, ADS1. If a timing other than the above is used, the correct conversion result may not be read. 194 User's Manual U16504EE1V1UD00 Chapter 12 A/D Converter 12.6 Cautions on Emulation To perform debugging with an in-circuit emulator, the D/A converter mode register (DAM0) must be set. DAM0 is a register used to set the I/O board (IE-78K0-NS-P04). 12.6.1 D/A converter mode register (DAM0) DAM0 is necessary if the power-fail detection function is used. Unless DAM0 is set, the power-fail detection function cannot be used. DAM0 is a write-only register. Because the IE-78K0-NS-P04 uses an external analog comparator and a D/A converter to implement part of the power-fail detection function, the reference voltage must be controlled. Therefore, set bit 0 (DACE) of DAM0 to 1 when using the power-fail detection function. Figure 12-13: D/A Converter Mode Register (DAM0) Format 7 DAM0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DACE R/W Address R/W FF9CH After Reset 00H DACE 0 1 Disabled Reference Voltage Control Enabled (when power-fail detection function is used) Cautions: 1. DAM0 is a special register that must be set when debugging is performed with an In-Circuit Emulator. Even if this register is used, the operation of the PD780828A Subseries is not affected. However, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. Bits 7 to 1 must be set to 0. User's Manual U16504EE1V1UD00 195 [MEMO] 196 User's Manual U16504EE1V1UD00 Chapter 13 Serial Interface SIO30 13.1 SIO30 Functions The SIO30 has the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used if serial transfer is not performed. For details, see 13.5.1 "Operation stop mode" on page 200. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK30), serial output line (SO30), and serial input line (SI30). Since simultaneous transmit and receive operations are enabled in 3-wire serial I/O mode, the processing time for data transfers is reduced. The first bit in the 8-bit data in serial transfers is fixed as the MSB. 3-wire serial I/O mode is useful for connection to a peripheral I/O device that includes a clock-synchronous serial interface, like a display controller, etc. For details see 13.5.2 "Three-wire serial I/O mode" on page 201. Figure 13-1 shows a block diagram of the SIO30. Figure 13-1: Block Diagram of SIO30 Internal bus 8 Direction control circuit 8 SI30/P37/S24 Serial I/O shift register 30 (SIO30) SO30/P36/S25 SCK30/P35/S26 Serial clock counter Serial clock control circuit Interruption request signal generator INTCSI30 fX/22 fX/23 fX/24 Selector Register CSIM30 CSIE30 MODE31 SCL301 SCL300 User's Manual U16504EE1V1UD00 197 Chapter 13 Serial Interface SIO30 13.2 SIO30 Configuration The SIO30 includes the following hardware. Table 13-1: Item Registers Control registers Composition of SIO30 Configuration Serial I/O shift register (SIO30) Serial operation mode register (CSIM30) (1) Serial I/O shift register (SIO30) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. SIO30 is set by an 8-bit memory manipulation instruction. When "1" is set to bit 7 (CSIE30) of the serial operation mode register (CSIM30), a serial operation can be started by writing data to or reading data from SIO30. When transmitting, data written to SIO30 is output via the serial output (SO30). When receiving, data is read from the serial input (SI30) and written to SIO30. The RESET signal resets the register value to 00H. Caution: Do not access SIO30 during a transmit operation unless the access is triggered by a transfer start. (Read is disabled when MODE30 = 0 and write is disabled when MODE30 = 1.) 13.3 List of SFRs (Special Function Registers) Table 13-2: SFR name Serial operation mode register Serial I/O shift register List of SFRs (Special Function Registers) Symbol CSIM30 SIO30 R/W R/W R/W Units available for bit manipulation 1-bit x 8-bit x x 16-bit Value after reset 00H 00H 198 User's Manual U16504EE1V1UD00 Chapter 13 Serial Interface SIO30 13.4 Serial Interface Control Register The SIO30 uses the following type of register for control functions. * Serial operation mode register (CSIM30) Serial operation mode register (CSIM30) This register is used to enable or disable the serial clock, selects operation modes, and defines specific operations. CSIM30 can be set via a 1-bit or 8-bit memory manipulation instruction. The RESET input sets the value to 00H. Figure 13-2: Format of Serial Operation Mode Register (CSIM30) <7> CSIM30 CSIE30 6 0 5 0 4 0 3 0 2 1 0 R/W Address FFA8H After Reset 00H MODE30 SCL301 SCL300 R/W Enable/disable specification for SIO30 CSIE30 0 1 Shift register operation Operation stop Operation enable Serial counter Clear Count operation enable Port Note 1 Port function Serial operation + port function MODE30 0 1 Transfer operation modes and flags Operation mode Transmit/receive mode Receive-only mode Note 2 Transfer start trigger Write to SIO30 Read from SIO30 SO30/P36 SO30 output Port function SCL301 0 0 1 1 SCL300 0 1 0 1 Clock selection (fX = 8.00 MHz) External clock input fX/22 fX/23 fX/24 Notes: 1. When CSIE30 = 0 (SIO30 operation stop status), the pins connected to SI30 and SO30 can be used for port functions. 2. When MODE30 = 1 (Receive mode), pin P36 can be used for port function. User's Manual U16504EE1V1UD00 199 Chapter 13 Serial Interface SIO30 13.5 Serial Interface Operations This section explains two modes of SIO30. 13.5.1 Operation stop mode This mode is used if the serial transfers are not performed to reduce power consumption. During the operation stop mode, the pins can be used as normal I/O ports as well. Register settings The operation stop mode can be set via the serial operation mode register (CSIM30). CSIM30 can be set via 1-bit or 8-bit memory manipulation instructions. The RESET input sets the value to 00H. Figure 13-3: Format of Serial Operation Mode Register (CSIM30) <7> CSIM30 CSIE30 6 0 5 0 4 0 3 0 2 1 0 R/W Address FFA8H After Reset 00H MODE30 SCL301 SCL300 R/W CSIE30 0 1 SIO30 Operation Enable/Disable Specification Shift register operation Operation stop Operation enable Serial counter Clear Count operation enable Port Port functionNote 1 Serial operation + port function Note: When CSIE30 = 0 (SIO30 operation stop status), the pins SI30, SO30 and SCK30 can be used for port functions. 200 User's Manual U16504EE1V1UD00 Chapter 13 13.5.2 Three-wire serial I/O mode Serial Interface SIO30 The three-wire serial I/O mode is useful when connecting a peripheral I/O device that includes a clock-synchronous serial interface, a display controller, etc. This mode executes the data transfer via three lines: a serial clock line (SCK30), serial output line (SO30), and serial input line (SI30). (1) Register settings The 3-wire serial I/O mode is set via serial operation mode register (CSIM30). CSIM30 can be set via 1-bit or 8-bit memory manipulation instructions. The RESET input set the value to 00H. Figure 13-4: Format of Serial Operation Mode Register (CSIM30) <7> CSIM30 CSIE30 6 0 5 0 4 0 3 0 2 1 0 R/W Address FFA8H After Reset 00H MODE30 SCL301 SCL300 R/W CSIE30 0 1 Enable/disable specification for SIO30 Shift register operation Operation stop Operation enable Serial counter Clear Port Port functionNote 1 Count operation enable Serial operation + port functionNote 2 Transfer operation modes and flags MODE30 0 1 SCL301 0 0 1 1 Operation mode Transmit/receive mode Receive-only mode Note 2 SCL300 0 1 0 1 Transfer start trigger Write to SIO30 Read from SIO30 Clock selection (fX = 8.00 MHz) External clock input fX/22 fX/23 fX/24 SO30/P36 SO30 output Port function Notes: 1. When CSIE30 = 0 (SIO30 operation stop status), the pins SI30, SO30 and SCK30 can be used for port functions. 2. When CSIE30 = 1 (SIO30 operation enabled status), the SI30 pin can be used as a port pin if only the send function is used, and the SO30 pin can be used as a port pin if only the receive-only mode is used. Caution: In the 3-wire serial I/O mode, set the port mode register (PM3) as required. Set the output latch of the port to 0. User's Manual U16504EE1V1UD00 201 Chapter 13 Serial Interface SIO30 Modes During serial clock output (master transmission or master reception) During serial clock input (slave transmission or slave reception) Transmit/receive mode Values PM35 = 0 P35 = 0 PM35 = 1 PM36 = 0 P36 = 0 Settings Sets P35 (SCK30) to output mode Sets output latch of P35 to 0 Sets P35 (SCK30) to input mode Sets P36 (SO30) to output mode Sets output latch of P36 to 0 Sets P37 (SI30) to input mode Receive mode PM37 = 1 (2) Communication Operations In the three-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received synchronized with the serial clock. The serial I/O shift register (SIO30) is shifted synchronized with the falling edge of the serial clock. The transmission data is held in the SO30 latch and is transmitted from the SO30 pin. The data is received via the SI30 pin synchronized with the rising edge of the serial clock is latched to SIO30. The completion of an 8-bit transfer automatically stops operation of SIO30 and sets a serial transfer completion flag. Figure 13-5: SCK30 SI30 SO30 Serial transfer completion flag 1 DI7 DO7 Timing of Three-wire Serial I/O Mode 2 DI6 DO6 3 DI5 DO5 4 DI4 DO4 5 DI3 DO3 6 DI2 DO2 7 DI1 DO1 8 DI0 DO0 Transfer completion Transfer starts in synchronized with the serial clock's falling edge 202 User's Manual U16504EE1V1UD00 Chapter 13 (3) Transfer start Serial Interface SIO30 A serial transfer starts when the following conditions have been satisfied and transfer data has been set to serial I/O shift register 30 (SIO30). * The SIO30 operation control bit must be set (CSIE = 1) * In Transmit/receive mode When CSIE30 = 1 and MODE30 = 0, transfer starts when writing to SIO30. * In Receive-only mode When CSIE30 = 1 and MODE30 = 1, transfer starts when reading from SIO30. Caution: After the data has been written to SIO30, the transfer will not start even if the CSIE30 bit value is set to "1". The completion of an 8-bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag. After an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. User's Manual U16504EE1V1UD00 203 [MEMO] User's Manual U16504EE1V1UD00 204 Chapter 14 Serial Interface SIO31 14.1 SIO31 Functions The SIO31 has the following three modes. * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode (1) Operation stop mode This mode is used if serial transfer is not performed. For details, see 14.5.1 "Operation stop mode" on page 210. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK31), serial output line (SO31), and serial input line (SI31). Since simultaneous transmit and receive operations are enabled in 3-wire serial I/O mode, the processing time for data transfers is reduced. The first bit in the 8-bit data in serial transfers is fixed as the MSB. 3-wire serial I/O mode is useful for connection to a peripheral I/O device that includes a clock-synchronous serial interface, like a display controller, etc. For details see 14.5.2 "Three-wire serial I/O mode" on page 211. (3) 2-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using two lines: a serial clock line (SCK31) and a serial data input/output line (SIO31). The first bit in the 8-bit data in serial transfers is fixed as the MSB. User's Manual U16504EE1V1UD00 205 Chapter 14 Serial Interface SIO31 Figure 14-1 shows a block diagram of the SIO31. Figure 14-1: Block Diagram of SIO31 Internal bus 8 Direction control circuit 8 SI31/P95/S18 Selector Serial I/O shift register 31 (SIO31) SO31/SIO31/P94/S19 SCK31/P93/S20 Serial clock counter Serial clock control circuit Interruption request signal generator INTCSI31 Selector TM50 fX/23 fX/27 Register CSIM31 CSIE31 MODE31 SCL311 SCL310 206 User's Manual U16504EE1V1UD00 Chapter 14 Serial Interface SIO31 14.2 SIO31 Configuration The SIO31 includes the following hardware. Table 14-1: Item Registers Control registers Composition of SIO31 Configuration Serial I/O shift register (SIO31) Serial operation mode register (CSIM31) Serial mode switch register (SIOSWI) (1) Serial I/O shift register (SIO31) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. SIO31 is set by an 8-bit memory manipulation instruction. When "1" is set to bit 7 (CSIE31) of the serial operation mode register (CSIM31), a serial operation can be started by writing data to or reading data from SIO31. When transmitting, data written to SIO31 is output via the serial output (SO31). When receiving, data is read from the serial input (SI31) and written to SIO31. The RESET signal resets the register value to 00H. Caution: Do not access SIO31 during a transmit operation unless the access is triggered by a transfer start. (Read is disabled when MODE31 = 0 and write is disabled when MODE31 = 1.) 14.3 List of SFRs (Special Function Registers) Table 14-2: SFR name Serial operation mode register Serial I/O shift register Serial mode switch register List of SFRs (Special Function Registers) Symbol CSIM31 SIO31 SIOSWI R/W R/W R/W R/W Units available for bit manipulation 1-bit x x 8-bit x x x 16-bit Value after reset 00H 00H 00H User's Manual U16504EE1V1UD00 207 Chapter 14 Serial Interface SIO31 14.4 Serial Interface Control Register The SIO31 uses the following type of register for control functions. * Serial operation mode register (CSIM31) * Serial mode switch register (SIOSWI) (1) Serial operation mode register (CSIM31) This register is used to enable or disable the serial clock, selects operation modes, and defines specific operations. CSIM31 can be set via an 1-bit or an 8-bit memory manipulation instruction. The RESET input sets the value to 00H. Figure 14-2: Format of Serial Operation Mode Register (CSIM31) <7> CSIM31 CSIE31 6 0 5 0 4 0 3 0 2 1 0 R/W Address FFAAH After Reset 00H MODE31 SCL311 SCL310 R/W Enable/disable specification for SIO31 CSIE31 0 1 Shift register operation Operation stop Operation enable Serial counter Clear Count operation enable Port Note 1 Port function Serial operation + port function MODE31 0 1 Transfer operation modes and flags Operation mode Transmit/receive mode Receive-only mode Note 2 Transfer start trigger Write to SIO31 Read from SIO31 SO31/SIO31/P94 SO31 output Port function SCL311 0 0 1 1 SCL310 0 1 0 1 Clock selection (fX = 8.00 MHz) External clock input TM50 fX/23 fX/27 Notes: 1. When CSIE31 = 0 (SIO31 operation stop status), the pins connected to SI31 and SO31 can be used for port functions. 2. When MODE31 = 1 (Receive mode), pin P94 can be used for port function. 208 User's Manual U16504EE1V1UD00 Chapter 14 (2) Serial mode switch register (SIOSWI) Serial Interface SIO31 This register is used to select the SIO31's 3-wire mode or 2-wire mode data communication mode. SIOSWI is set by an 1-bit or 8-bit memory manipulation instruction. The RESET input sets SIOSWI to 00H. Figure 14-3: Format of Serial Mode Switch Register (SIOSWI) 7 SIOSWI 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R/W Address FFABH After Reset 00H SIOSWI R/W SIOSWI 0 1 3-wire mode (reset) 2-wire mode SIO31 - Serial mode switch The following operation modes and start trigger have to be set for the usage of the 3-wire mode or the 2-wire mode data communication mode. Table 14-3: MODE31 0 1 0 1 3-wire or 2-wire mode of SIO31 (SIOSWI) 2-wire mode Operating Modes and Start Trigger Operation Mode Flag Operation mode Start trigger Port 94 SO31 SI31 SO31 Port function Port 93 Port function Port function SI31 SI31 Transmit/Receive mode SIO31 write Receive mode SIO31 read 3-wire mode Transmit/Receive mode SIO31 write Receive mode SIO31 read User's Manual U16504EE1V1UD00 209 Chapter 14 Serial Interface SIO31 14.5 Serial Interface Operations This section explains two modes of SIO31. 14.5.1 Operation stop mode This mode is used if the serial transfers are not performed to reduce power consumption. During the operation stop mode, the pins can be used as normal I/O ports as well. Register settings The operation stop mode can be set via the serial operation mode register (CSIM31). CSIM31 can be set via 1-bit or 8-bit memory manipulation instructions. The RESET input sets the value to 00H. Figure 14-4: Format of Serial Operation Mode Register (CSIM31) <7> CSIM31 CSIE31 6 0 5 0 4 0 3 0 2 1 0 R/W Address FFAAH After Reset 00H MODE31 SCL311 SCL310 R/W CSIE31 0 1 SIO31 Operation Enable/Disable Specification Shift register operation Operation stop Operation enable Serial counter Clear Port Port functionNote 1 Count operation enable Serial operation + port functionNote 2 Notes: 1. When CSIE31 = 0 (SIO31 operation stop status), the pins SI31, SO31 and SCK31 can be used for port functions. 2. When CSIE31 = 1 (SIO31 operation enabled status), the SI31 pin can be used as a port pin if only the send function is used, and the SO31 pin can be used as a port pin if only the receive-only mode is used. 210 User's Manual U16504EE1V1UD00 Chapter 14 14.5.2 Three-wire serial I/O mode Serial Interface SIO31 The three-wire serial I/O mode is useful when connecting a peripheral I/O device that includes a clock-synchronous serial interface, a display controller, etc. This mode executes the data transfer via three lines: a serial clock line (SCK31), serial output line (SO31), and serial input line (SI31). (1) Register settings The 3-wire serial I/O mode is set via serial operation mode register (CSIM31). CSIM31 can be set via 1-bit or 8-bit memory manipulation instructions. The RESET input set the value to 00H. Figure 14-5: Format of Serial Operation Mode Register (CSIM31) <7> CSIM31 CSIE31 6 0 5 0 4 0 3 0 2 1 0 R/W Address FFAAH After Reset 00H MODE31 SCL311 SCL310 R/W CSIE31 0 1 Enable/disable specification for SIO31 Shift register operation Operation stop Operation enable Serial counter Clear Port Port functionNote 1 Count operation enable Serial operation + port functionNote 2 Transfer operation modes and flags MODE31 0 1 SCL311 0 0 1 1 SCL310 0 1 0 1 Operation mode Transmit/transmit and receive mode Receive-only mode Transfer start trigger Write to SIO31 Read from SIO31 Clock selection External clock input to SCK31 TM50 fX/23 fX/27 SO31 Output Normal output Fixed a low level Notes: 1. When CSIE31 = 0 (SIO31 operation stop status), the pins SI31, SO31 and SCK31 can be used for port functions. 2. When CSIE31 = 1 (SIO31 operation enabled status), the SI31 pin can be used as a port pin if only the send function is used, and the SO31 pin can be used as a port pin if only the receive-only mode is used. Caution: In the 3-wire serial I/O mode, set the port mode register (PM9) as required. Set the output latch of the port to 0. User's Manual U16504EE1V1UD00 211 Chapter 14 Serial Interface SIO31 Modes During serial clock output (master transmission or master reception) During serial clock input (slave transmission or slave reception) Transmit/receive mode Values PM93 = 0 P93 = 0 PM93 = 1 PM94 = 0 P94 = 0 Settings Sets P93 (SCK31) to output mode Sets output latch of P95 to 0 Sets P93 (SCK31) to input mode Sets P94 (SO31) to output mode Sets output latch of P94 to 0 Sets P93 (SI31) to input mode Receive mode PM93 = 1 (2) Serial mode switch register (SIOSWI) This register is used to select the SIO31's 3-wire mode or 2-wire mode data communication mode. SIOSWI is set by an 1-bit or 8-bit memory manipulation instruction. The RESET input sets SIOSWI to 00H. Figure 14-6: Format of Serial Mode Switch Register (SIOSWI) 7 SIOSWI 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R/W Address FFABH After Reset 00H SIOSWI R/W SIOSWI 0 1 3-wire mode (reset) 2-wire mode SIO31 - Serial mode switch The following operation modes and start trigger have to be set for the usage of the 3-wire mode. Table 14-4: MODE31 0 1 3-wire or 2-wire mode of SIO31 (SIOSWI) 3-wire mode Operating Modes and Start Trigger Operation Mode Flag Operation mode Start trigger Port 94 SO31 Port function SI31 SI31 Port 93 Transmit/Receive mode SIO31 write Receive mode SIO31 read 212 User's Manual U16504EE1V1UD00 Chapter 14 14.5.3 Two-wire serial I/O mode Serial Interface SIO31 The 2-wire serial I/O mode is useful when connecting a peripheral I/O device that includes a clock-synchronous serial interface, a display controller, etc. This mode executes the data transfer via two lines: a serial clock line (SCK31), serial output line (SO31), and serial input/output line (SIO31). (1) Register settings The 2-wire serial I/O mode is set via serial operation mode register 31 (CSIM31). CSIM31 can be set by an 1-bit or 8-bit memory manipulation instructions. The RESET input sets CSIM31 to 00H. Figure 14-7: Format of Serial Operation Mode Register (CSIM31) <7 CSIM31 CSIE31 6 0 5 0 4 0 3 0 2 1 0 R/W Address FFAAH After Reset 00H MODE31 SCL311 SCL310 R/W CSIE31 0 1 Enable/disable specification for SIO31 Shift register operation Operation stop Operation enable Serial counter Clear Count operation enable Port Port functionNote 1 Serial operation + port function MODE31 0 1 SCL311 0 0 1 1 SCL310 0 1 0 1 Transfer operation modes and flags Operation mode Transmit/transmit and receive mode Receive-only mode Transfer start trigger Write to SIO31 Read from SIO31 Clock selection External clock input to SCK31 TM50 fX/23 fX/27 SO31 Output SIO31 SI31 Note: When CSIE31 = 0 (SIO31 operation stop status), the pins SI31, SO31 and SCK31 can be used for port functions. Caution: In the 2-wire serial I/O mode, set the port mode register (PM9) as required. Set the output latch of the port to 0. User's Manual U16504EE1V1UD00 213 Chapter 14 Serial Interface SIO31 Modes During serial clock output (master transmission or master reception) During serial clock input (slave transmission or slave reception) Values PM93 = 0 P93 = 0 PM93 = 1 PM94 = 0 Settings Sets P93 (SCK31) to output mode Sets output latch of P95 to 0 Sets P93 (SCK31) to input mode Sets P94 (SO31) to output mode (Transmit mode) Sets P94 (SIO31) to input mode (Receive mode) Sets output latch of P94 to 0 Transmit/receive mode PM94 = 1 P94 = 0 (2) Serial mode switch register (SIOSWI) This register is used to select the SIO31's 3-wire mode or 2-wire mode data communication mode. SIOSWI is set by an 1-bit or 8-bit memory manipulation instruction. The RESET input sets SIOSWI to 00H. Figure 14-8: Format of Serial Mode Switch Register (SIOSWI) 7 SIOSWI 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R/W Address FFABH After Reset 00H SIOSWI R/W SIOSWI 0 1 3-wire mode (reset) 2-wire mode SIO31 - Serial mode switch The following operation modes and start trigger have to be set for the usage of the 3-wire mode. Table 14-5: MODE31 0 1 3-wire or 2-wire mode of SIO31 (SIOSWI) 2-wire mode Operating Modes and Start Trigger Operation Mode Flag Operation mode Start trigger Port 94 SO31 SI31 Port 93 Port function Port function Transmit/Receive mode SIO31 write Receive mode SIO31 read 214 User's Manual U16504EE1V1UD00 Chapter 14 (3) 3-wire Communication Operations Serial Interface SIO31 In the three-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received synchronized with the serial clock. The serial I/O shift register (SIO31) is shifted synchronized with the falling edge of the serial clock. The transmission data is held in the SO31 latch and is transmitted from the SO31 pin. The data is received via the SI31 pin synchronized with the rising edge of the serial clock is latched to SIO31. The completion of an 8-bit transfer automatically stops operation of SIO31 and sets a serial transfer completion flag. Figure 14-9: SCK31 SI31 SO31 Serial transfer completion flag 1 DI7 DO7 Timing of Three-wire Serial I/O Mode 2 DI6 DO6 3 DI5 DO5 4 DI4 DO4 5 DI3 DO3 6 DI2 DO2 7 DI1 DO1 8 DI0 DO0 Transfer completion Transfer starts in synchronized with the serial clock's falling edge (4) 2-wire Communication Operations In the two-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received synchronized with the serial clock. The serial I/O shift register 31 (SIO31) is shifted synchronized with the falling edge of the serial clock. The transmission data is held in the SIO31 latch and is transmitted from the SIO31 pin. The data is received via the SIO31 pin synchronized with the rising edge of the serial clock is latched to SIO31. The completion of an 8-bit transfer automatically stops operation of SIO31 and sets interrupt request flag. Figure 14-10: SCK31 Data input SIO31 Data output SIO31 Serial transfer completion flag 1 DI7 DO7 Timing of Two-wire Serial I/O Mode 2 DI6 DO6 3 DI5 DO5 4 DI4 DO4 5 DI3 DO3 6 DI2 DO2 7 DI1 DO1 8 DI0 DO0 Transfer completion Transfer starts in synchronized with the serial clock's falling edge User's Manual U16504EE1V1UD00 215 Chapter 14 Serial Interface SIO31 (5) Transfer start A serial transfer starts when the following conditions have been satisfied and transfer data has been set to serial I/O shift register 31 (SIO31). * The SIO31 operation control bit must be set (CSIE = 1) * In Transmit/receive mode When CSIE31 = 1 and MODE31 = 0, transfer starts when writing to SIO31. * In Receive-only mode When CSIE31 = 1 and MODE31 = 1, transfer starts when reading from SIO31. Caution: After the data has been written to SIO31, the transfer will not start even if the CSIE31 bit value is set to "1". The completion of an 8-bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag. After an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. 216 User's Manual U16504EE1V1UD00 Chapter 15 Serial Interface Channel UART 15.1 UART Functions The serial interface UART has the following modes. (1) Operation stop mode This mode is used if the serial transfer is performed to reduce power consumption. For details, see 16.5.1 Operation Stop Mode. (2) Asynchronous serial interface (UART) mode This mode enables the full-duplex operation where one byte of data is transmitted and received after the start bit. The on-chip dedicated UART baud rate generator enables communications using a wide range of selectable baud rates. For details, see 16.5.2 Asynchronous Serial Interface (UART) Mode. Figure 14-1 shows a block diagram of the UART macro. Figure 15-1: Block Diagram of UART Internal bus ASIM0 Receive RXB0 buffer TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 RXS0 RXD/P62 Receive shift register ASIS0 PE0 FE0 OVE0 TXS0 Transmit shift register TXD/P63 Receive control parity check Transmit control parity INTSER0 addition INTST0 INTSR0 Baud rate generator f X /2 - f X /28 User's Manual U16504EE1V1UD00 217 Chapter 15 Serial Interface Channel UART 15.2 UART Configuration The UART includes the following hardware. Table 15-1: Item Configuration of UART Configuration Transmit shift register 1 (TXS0) Registers Receive shift register 1 (RXS0) Receive buffer register (RXB0) Asynchronous serial interface mode register (ASIM0) Control registers Asynchronous serial interface status register (ASIS0) Baud rate generator control register (BRGC0) (1) Transmit shift register 1 (TXS0) This register is for setting the transmit data. The data is written to TXS0 for transmission as serial data. When the data length is set as 7 bits, bits 0 to 6 of the data written to TXS0 are transmitted as serial data. Writing data to TXS0 starts the transmit operation. TXS0 can be written via 8-bit memory manipulation instructions. It cannot be read. When RESET is input, its value is FFH. Cautions: 1. Do not write to TXS0 during a transmit operation. 2. The same address is assigned to TXS0 and the receive buffer register (RXB0). A read operation reads values from RXB0. (2) Receive shift register 1 (RXS0) This register converts serial data input via the RXD pin to parallel data. When one byte of the data is received at this register, the receive data is transferred to the receive buffer register (RXB0). RXS0 cannot be manipulated directly by a program. (3) Receive buffer register (RXB0) This register is used to hold receive data. When one byte of data is received, one byte of new receive data is transferred from the receive shift register (RXS0). When the data length is set as 7 bits, receive data is sent to bits 0 to 6 of RXB0. The MSB must be set to "0" in RXB0. RXB0 can be read to via 8-bit memory manipulation instructions. It cannot be written to. When RESET is input, its value is FFH. Caution: The same address is assigned to RXB0 and the transmit shift register (TXS0). During a write operation, values are written to TXS0. 218 User's Manual U16504EE1V1UD00 Chapter 15 (4) Transmission control circuit Serial Interface Channel UART The transmission control circuit controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to the transmit shift register (TXS0), based on the values set to the asynchronous serial interface mode register (ASIM0). (5) Reception control circuit The reception control circuit controls the receive operations based on the values set to the asynchronous serial interface mode register (ASIM0). During a receive operation, it performs error checking, such as parity errors, and sets various values to the asynchronous serial interface status register (ASIS0) according to the type of error that is detected. 15.3 List of SFRS (Special Function Registers) Table 15-2: List of SFRs (Special Function Registers) Units available for bit manipulation 1-bit 8-bit x x x x 16-bit 00H Value when reset FFH SFR name Symbol R/W Transmit shift register Receive buffer register Asynchronous serial interface mode register TXS0 RXB0 ASIM0 W R R/W R R/W x - Asynchronous serial interface status register ASIS0 Baud rate generator control register BRGC0 User's Manual U16504EE1V1UD00 219 Chapter 15 Serial Interface Channel UART 15.4 Serial Interface Control Registers The UART uses the following three types of registers for control functions. * Asynchronous serial interface mode register (ASIM0) * Asynchronous serial interface status register (ASIS0) * Baud rate generator control register (BRGC0) (1) Asynchronous serial interface mode register (ASIM0) This is an 8-bit register that controls the UART serial transfer operation. ASIM0 can be set by 1-bit or 8-bit memory manipulation instructions. RESET input sets the value to 00H. Figure 14-2 shows the format of ASIM0. Figure 15-2: Format of Asynchronous Serial Interface Mode Register (ASIM0) (1/2) <7> ASIM0 TXE0 <6> RXE0 5 PS01 4 PS00 3 CL0 2 SL0 1 ISRM0 0 0 R/W Address R/W FFA0H After Reset 00H TXE0 0 0 1 1 RXE0 0 1 0 1 Operation mode Operation stop UART0 mode (receive only) UART0 mode (transmit only) UART0 mode (transmit and receive) RXD0/P62 pin function TXD0/P63 pin function Port function Serial operation Port function Serial operation Port function Port function Serial operation Serial operation PS01 0 0 1 1 PS00 0 1 0 1 No parity Parity bit specification Zero parity always added during transmission No parity detection during reception (parity errors do not occur) Odd parity Even parity CL0 0 1 7 bits 8 bits Character length specification 220 User's Manual U16504EE1V1UD00 Chapter 15 Figure 15-2: Serial Interface Channel UART Format of Asynchronous Serial Interface Mode Register (ASIM0) (2/2) SL0 0 1 1 bit 2 bits Stop bit length specification for transmit data ISRM0 0 1 Receive completion interrupt control when error occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Caution: Do not switch the operation mode until the current serial transmit/receive operation has stopped. User's Manual U16504EE1V1UD00 221 Chapter 15 Serial Interface Channel UART (2) Asynchronous serial interface status register (ASIS0) When a receive error occurs during UART mode, this register indicates the type of error. ASIS0 can be read using an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 15-3: Format of Asynchronous Serial Interface Status Register (ASIS0) 7 ASIS0 0 6 0 5 0 4 0 3 0 2 PE0 1 FE0 0 OVE0 R/W Address R FFA1H After Reset 00H PE0 0 1 No parity error Parity error (Incorrect parity bit detected) Parity error flag FE0 0 1 No framing error Framing errorNote 1 (Stop bit not detected) Framing error flag FE0 0 1 No overrun error Overrun error flag Overrun errorNote 2 (Next receive operation was completed before data was read from receive buffer register) Notes: 1. Even if a stop bit length of two bits has been set to bit 2 (SL0) in the asynchronous serial interface mode register (ASIM0), the stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of the receive buffer register (RXB0) when an overrun error has occurred. Until the contents of RXB0 are read, further overrun errors will occur when receiving data. 222 User's Manual U16504EE1V1UD00 Chapter 15 (3) Serial Interface Channel UART Baud rate generator control register (BRGC0) This register sets the serial clock for UART. BRGC0 can be set via an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 14-4 shows the format of BRGC0. Figure 15-4: Format of Baud Rate Generator Control Register (BRGC0) (1/2) 7 BRGC0 0 6 TPS02 5 TPS01 4 TPS00 3 MDL03 2 MDL02 1 MDL01 0 MDL00 R/W Address R/W FFA2H After Reset 00H (fX = 8.00 MHz) TPS02 0 0 0 0 1 1 1 1 TPS01 0 0 1 1 0 0 1 1 TPS00 0 1 0 1 0 1 0 1 Source clock selection for 5-bit counter fX/2 1 n 1 2 3 4 5 6 7 8 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 User's Manual U16504EE1V1UD00 223 Chapter 15 Serial Interface Channel UART Figure 15-4: Format of Baud Rate Generator Control Register (BRGC0) (2/2) MDL03 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MDL02 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MDL01 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MDL00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input clock selection for baud rate generator fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 Setting prohibited k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - Caution: Writing to BRGC0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. Therefore, do not write to BRGC0 during a communication operation. Remarks: 1. fSCK: Source clock for 5-bit counter 2. n: Value set via TPS00 to TPS02 (1 n 8) 3. k: Value set via MDL00 to MDL03 (0 k 14) 224 User's Manual U16504EE1V1UD00 Chapter 15 Serial Interface Channel UART 15.5 Serial Interface Operations This section explains the different modes of the UART. 15.5.1 Operation stop mode This mode is used when serial transfer is performed to reduce power consumption. In the operation stop mode, pins can be used as ordinary ports. Register settings Operation stop mode settings are made via the asynchronous serial interface mode register (ASIM0). TXE0 and RXE0 must be set to 0. Figure 15-5: Register Settings <7> ASIM0 TXE0 <6> RXE0 5 PS01 4 PS00 3 CL0 2 SL0 1 ISRM0 0 0 R/W Address R/W FFA0H After Reset 00H TXE0 0 0 1 1 RXE0 0 1 0 1 Operation mode Operation stop UART0 mode (receive only) UART0 mode (transmit only) UART0 mode (transmit and receive) RXD0/P62 pin function TXD0/P63 pin function Port function Serial operation Port function Serial operation Port function Port function Serial operation Serial operation Caution: Do not switch the operation mode until the current serial transmit/receive operation has stopped. User's Manual U16504EE1V1UD00 225 Chapter 15 Serial Interface Channel UART 15.5.2 Asynchronous serial interface (UART) mode This mode enables full-duplex operation where one byte of the data is transmitted or received after the start bit. The on-chip dedicated UART baud rate generator enables communications by using a wide range of selectable baud rates. (1) Register settings The UART mode settings are made via the asynchronous serial interface mode register (ASIM0), asynchronous serial interface status register (ASIS0), and the baud rate generator control register (BRGC0). (a) Asynchronous serial interface mode register (ASIM0) ASIM0 can be set by 1-bit or 8-bit memory manipulation instructions. When RESET is input, its value is 00H. Figure 15-6: Format of Asynchronous Serial Interface Mode Register (ASIM0) (1/2) <7> ASIM0 TXE0 <6> RXE0 5 PS01 4 PS00 3 CL0 2 SL0 1 ISRM0 0 0 R/W Address R/W FFA0H After Reset 00H TXE0 0 0 1 1 RXE0 0 1 0 1 Operation mode Operation stop UART0 mode (receive only) UART0 mode (transmit only) UART0 mode (transmit and receive) RXD0/P62 pin function TXD0/P63 pin function Port function Serial operation Port function Serial operation Port function Port function Serial operation Serial operation PS01 0 0 1 1 PS00 0 1 0 1 No parity Parity bit specification Zero parity always added during transmission No parity detection during reception (parity errors do not occur) Odd parity Even parity CL0 0 1 7 bits 8 bits Character length specification 226 User's Manual U16504EE1V1UD00 Chapter 15 Figure 15-6: Serial Interface Channel UART Format of Asynchronous Serial Interface Mode Register (ASIM0) (2/2) SL0 0 1 1 bit 2 bits Stop bit length specification for transmit data ISRM0 0 1 Receive completion interrupt control when error occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Caution: Do not switch the operation mode until the current serial transmit/receive operation has stopped. User's Manual U16504EE1V1UD00 227 Chapter 15 Serial Interface Channel UART (b) Asynchronous serial interface status register (ASIS0) ASIS0 can be read using an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 15-7: Format of Asynchronous Serial Interface Status Register (ASIS0) 7 ASIS0 0 6 0 5 0 4 0 3 0 2 PE0 1 FE0 0 OVE0 R/W Address R FFA1H After Reset 00H PE0 0 1 No parity error Parity error (Incorrect parity bit detected) Parity error flag FE0 0 1 No framing error Framing errorNote 1 (Stop bit not detected) Framing error flag OVE0 0 1 No overrun error Overrun error flag Overrun errorNote 2 (Next receive operation was completed before data was read from receive buffer register) Notes: 1. Even if a stop bit length of two bits has been set to bit 2 (SL0) in the asynchronous serial interface mode register (ASIM0), the stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of the receive buffer register (RXB0) when an overrun error has occurred. Until the contents of RXB0 are read, further overrun errors will occur when receiving data. 228 User's Manual U16504EE1V1UD00 Chapter 15 Serial Interface Channel UART (c) Baud rate generator control register (BRGC0) BRGC0 can be set via an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 15-8: Format of Baud Rate Generator Control Register (BRGC0) (1/2) 7 BRGC0 0 6 TPS02 5 TPS01 4 TPS00 3 MDL03 2 MDL02 1 MDL01 0 MDL00 R/W Address R/W FFA2H After Reset 00H (fX = 8.00 MHz) TPS02 0 0 0 0 1 1 1 1 TPS01 0 0 1 1 0 0 1 1 TPS00 0 1 0 1 0 1 0 1 Source clock selection for 5-bit counter fX/21 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 n 1 2 3 4 5 6 7 8 User's Manual U16504EE1V1UD00 229 Chapter 15 Serial Interface Channel UART Figure 15-8: Format of Baud Rate Generator Control Register (BRGC0) (2/2) MDL03 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MDL02 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MDL01 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MDL00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input clock selection for baud rate generator fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 Setting prohibited k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - Caution: Writing to BRGC0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. Therefore, do not write to BRGC0 during a communication operation. Remarks: 1. fSCK: Source clock for 5-bit counter 2. n: Value set via TPS00 to TPS02 (1 n 8) 3. k: Value set via MDL00 to MDL03 (0 k 14) 230 User's Manual U16504EE1V1UD00 Chapter 15 Serial Interface Channel UART The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. * Baud rate setting The main system clock is divided to generate the transmit/receive clock. The baud rate generated by the main system clock is determined according to the following formula. [Baud rate] = fX 2n+1(k + 16) [kbps] fX : Oscillation frequency of main system clock in MHz n : Value set via TPS00 to TPS02 (1 n 8) For details, see Table 15-3. k : Value set via MDL00 to MDL02 (0 k 14) in register BRGC0 The relation between the 5-bit counter's source clock assigned to bits 4 to 6 (TPS00 to TPS02) of BRGC0 and the "n" value in the above formula is shown in Figure 15-4, "Format of Baud Rate Generator Control Register (BRGC0) (1/2)," on page 223. Table 15-3: TPS02 0 0 0 0 1 1 1 1 TPS01 0 0 1 1 0 0 1 1 Relation between 5-bit Counter's Source Clock and "n" Value TPS00 0 1 0 1 0 1 0 1 Source clock selection for 5-bit counter fX/21 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 n 1 2 3 4 5 6 7 8 Remark: fX: Oscillation frequency of main system clock. User's Manual U16504EE1V1UD00 231 Chapter 15 Serial Interface Channel UART * Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter's division rate [1/(16 + k)]. Table 15-4 describes the relation between the main system clock and the baud rate and Figure 14-9 shows an example of a baud rate error tolerance range. Table 15-4: Baud rate (bps) 600 1200 2400 4800 9600 19200 31250 38400 76800 115200 Relation between Main System Clock and Baud Rate fX = 8.000 MHz BRGCO 7AH 6AH 5AH 4AH 3AH 2AH 20H 1AH 0AH 01H ERR (%) 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 0.16 fX = 5.000 MHz BRGCO 70H 60H 50H 40H 30H 20H 14H 10H 00H ERR (%) 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 fX = 4.1943 MHz BRGCO 6BH 5BH 4BH 3BH 2BH 1BH 11H 0BH ERR (%) 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 - fX = 8.386 MHz BRGCO 7BH 6BH 5BH 4BH 3BH 2BH 21H 1BH 0BH 02H ERR (%) 1.10 1.10 1.10 1.10 1.10 -1.3 1.10 1.10 1.10 1.03 Remarks: 1. fX: Oscillation frequency of main system clock 2. n: Value set via TPS00 to TPS02 (1 n 8) 3. k: Value set via MDL00 to MDL03 (0 k 14) Figure 15-9: Error Tolerance (when k = 0), including Sampling Errors Ideal sampling point 32T 64T 256T 288T 320T 352T 304T Basic timing (clock cycle T) High-speed clock (clock cycle T') enabling normal reception Low-speed clock (clock cycle T") enabling normal reception START D0 D7 P 15.5T 336T STOP START 30.45T START D0 60.9T D0 33.55T 67.1T D7 P STOP 304.5T 15.5T Sampling error 0.5T STOP D7 301.95T P 335.5T Remark: T: 5-bit counter's source clock cycle Baud rate error tolerance (when k = 0) = 15.5 x 100 320 = 4.8438 (%) 232 User's Manual U16504EE1V1UD00 Chapter 15 (2) Communication operations (a) Data format Serial Interface Channel UART As shown in Figure 15-10, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. The asynchronous serial interface mode register (ASIM0) is used to set the character bit length, parity selection, and stop bit length within each data frame. Figure 15-10: Format of Transmit/Receive Data in Asynchronous Serial Interface 1 data frame Start bit Parity bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 * * * * Start bit............. Character bits... Parity bit........... Stop bit(s)........ 1 bit 7 bits or 8 bits Even parity, odd parity, zero parity, or no parity 1 bit or 2 bits When "7 bits" is selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are valid. In this case during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to "0". The asynchronous serial interface mode register (ASIM0) and the baud rate generator control register (BRGC0) are used to set the serial transfer rate. If a receive error occurs, information about the receive error can be recognized by reading the asynchronous serial interface status register (ASIS0). User's Manual U16504EE1V1UD00 233 Chapter 15 Serial Interface Channel UART (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. When zero parity or no parity is set, errors are not detected. * Even parity * During transmission The number of bits in transmit data that includes a parity bit is controlled so that there are an even number of "1" bits. The value of the parity bit is as follows. If the transmit data contains an odd number of "1" bits: the parity bit value is "1". If the transmit data contains an even number of "1" bits: the parity bit value is "0" * During reception The number of "1" bits is counted among the transfer data that include a parity bit, and a parity error occurs when the result is an odd number. * Odd parity * During transmission The number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of "1" bits. The value of the parity bit is as follows. If the transmit data contains an odd number of "1" bits: the parity bit value is "0" If the transmit data contains an even number of "1" bits: the parity bit value is "1" * During reception The number of "1" bits is counted among the transfer data that include a parity bit, and a parity error occurs when the result is an even number. * Zero parity During transmission, the parity bit is set to "0" regardless of the transmit data. During reception, the parity bit is not checked. Therefore, no parity errors will occur regardless of whether the parity bit is a "0" or a "1". * No parity No parity bit is added to the transmit data. During reception, receive data is regarded as having no parity bit. Since there is no parity bit, no parity errors will occur. 234 User's Manual U16504EE1V1UD00 Chapter 15 (c) Transmission Serial Interface Channel UART The transmit operation is started when transmit data is written to the transmit shift register (TXS0). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXS0, thereby emptying TXS0, after which a transmit completion interrupt (INTST0) is issued. The timing of the transmit completion interrupt is shown in Figure 15-11. Figure 15-11: Timing of Asynchronous Serial Interface Transmit Completion Interrupt (1) Stop bit length: 1 bit TXD (output) START D0 D1 D2 D6 D7 Parity STOP INTST0 (2) Stop bit length: 2 bits TXD (output) START D0 D1 D2 D6 D7 Parity STOP INTST0 Caution: Do not write to the asynchronous serial interface mode register (ASIM0) during a transmit operation. Writing to ASIM0 during a transmit operation may disable further transmit operations (in such cases, enter a RESET to restore normal operation). Whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt (INTST0) or the interrupt request flag (STIF) that is set by INTST0. User's Manual U16504EE1V1UD00 235 Chapter 15 Serial Interface Channel UART (d) Reception The receive operation is enabled when bit 6 (RXE0) of the asynchronous serial interface mode register (ASIM0) is set to "1", and input data via RXD pin is sampled. The serial clock specified by ASIM0 is used when sampling the RXD pin. When the RXD pin goes low, the 5-bit counter begins counting, the start timing signal for data sampling is output if half of the specified baud rate time has elapsed. If the sampling of the RXD0 pin input of this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. After the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. Once the reception of one data frame is completed, the receive data in the shift register is transferred to the receive buffer register (RXB0) and a receive completion interrupt (INTSR0) occurs. Even if an error has occurred, the receive data in which the error occurred is still transferred to RXB0 and INTSR0 occurs (see Figure 14-9). If the RXE0 bit is reset (to "0") during a receive operation, the receive operation is stopped immediately. At this time, neither the contents of RXB0 and ASIS0 will change, nor does INTSR0 or INTSER0 occur. Figure 15-12 shows the timing of the asynchronous serial interface receive completion interrupt. Figure 15-12: Timing of Asynchronous Serial Interface Receive Completion Interrupt RXD (input) START D0 D1 D2 D6 D7 Parity STOP INTSR0 Caution: Be sure to read the contents of the receive buffer register (RXB0) even when a receive error has occurred. Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXB0 are read. 236 User's Manual U16504EE1V1UD00 Chapter 15 (e) Receive errors Serial Interface Channel UART Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of the data reception, an error flag is set to the asynchronous serial interface status register (ASIS0), a receive error interrupt (INTSER0) will occur. Receive error interrupts are generated before receive interrupts (INTSR0). Table 15-5 lists the causes of receive errors. As part of the receive error interrupt (INTSER0) servicing, the contents of ASIS0 can be read to determine which type of error occurred during the receive operation (see Table 14-5 and Figure 15-13). The content of ASIS0 is reset (to "0") if the receive buffer register (RXB0) is read or when the next data is received (if the next data contains an error, another error flag will be set). Table 15-5: Receive error Parity error Causes of Receive Errors Cause ASIS0 value 04H 02H 01H Parity specified during transmission does not match parity of receive data Framing error Stop bit was not detected Overrun error Reception of the next data was completed before data was read from the receive buffer register Figure 15-13: Receive Error Timing RXD0 (input) START D0 D1 D2 D6 D7 Parity STOP INTSR0 INTSER0 INTSER0 (When parity error occurs) Cautions: 1. The contents of ASIS0 are reset (to "0") when the receive buffer register (RXB0) is read or when the next data is received. To obtain information about the error, be sure to read the contents of ASIS0 before reading RXB0. 2. Be sure to read the contents of the receive buffer register (RXB0) even when a receive error has occurred. Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXB0 are read. User's Manual U16504EE1V1UD00 237 Chapter 15 Serial Interface Channel UART 15.6 Behavior of UART during Standby of the Controller Serial transfer operations can be performed during HALT mode of the controller. During STOP mode, serial transfer operations are stopped and the values in the asynchronous serial interface mode register (ASIM0), the transmit shift register (TXS0), the receive shift register (RXS0), and the receive buffer register (RXB0) remain as they were just before the clock was stopped. Output from the TXD pin retains the current data if the clock is stopped (if the system enters STOP mode) during a transmit operation. If the clock is stopped during a receive operation, the data received before the clock was stopped is retained and all subsequent operations are stopped. The receive operation can be restarted once the clock is restarted. 238 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Table 16-1: Feature Protocol Baudrate Bus line control Clock Data storage Outline of the Function Details CAN2.0 with active extended frame capability (Bosch specification 2.0 part B) Max. 500 Kbps at 8 MHz clock supply CMOS in / out for external transceiver Selected by register CPU RAM area with shared access DCAN uses up to 288 byte of RAM Unused bytes can be used by CPU for other tasks Received messages will be stored in RAM area depending on message identifier Transmit messages have two dedicated buffers in RAM area One input receive shadow buffer (not readable by user) Up to 16 receive message objects including 2 masks Two transmit channels Unique identifier on all 16 receive message objects Up to 2 message objects with mask Global mask for all messages SFR access for general control Transmit interrupt for each channel One receive interrupt with enable control for each message One error interrupt Support of time stamp and global time system Programmable single shot mode Readable error counters "Valid protocol activity flag" for verification of bus connection "Receive only" mode for automatic baudrate detection Sleep mode: Wake up from CAN bus Stop mode: No wake-up from CAN bus Message organisation Message number Message sorting DCAN protocol Interrupt Time functions Diagnostic Power down modes User's Manual U16504EE1V1UD00 239 Chapter 16 CAN Controller 16.1 CAN Protocol CAN is an abbreviation of "Controller Area Network", and is a class C high speed multiplexed communication protocol. CAN is specified by Bosch in the CAN specification 2.0 from September 1991 and is standardized in ISO-11898 (International Organization for Standardization) and SAE (Society of Automotive Engineers). 16.1.1 Protocol Mode Function (1) Standard format mode * This mode supports an 11-bit message identifier thus making it possible to differentiate between 2048 types of messages. (2) Extended format mode * In the extended format mode, the identifier has 29 bits. It is built by the standard identifier (11 bits) and an extended identifier (18 bits). * When the IDE bits of the arbitration field is "recessive", the frame is sent in the extended format mode. * When a message in extended format mode and a remote frame in standard format mode are simultaneously transmitted, the node transmitting the message with the standard mode wins the arbitration. (3) Bus values * The bus can have one of two complementary logical values: "dominant" or "recessive". During simultaneous transmission of "dominant" and "recessive" bits, the resulting bus value will be "dominant" (non destructive arbitration). * For example, in case of a wired-AND implementation of the bus, the "dominant" level would be represented by a logical "0" and the "recessive" level by a logical "1". This specific representation is used in this manual. * Physical states (e.g. electrical voltage, light) that represent the logical levels are not given in this document. 16.1.2 Message Format The CAN protocol message supports different types of frames. The types of frames are listed below: * Data frame: * Remote frame: * Error frame: * Overload frame: Carries the data from a transmitter to the receiver. Transmission demand frame from the requesting node. Frame sent on error detection. Frame sent when a data or remote frame would be overwritten by the next one before the receiving node could process it. The reception side did not finish its operations on the reception of the previously received frame yet. 240 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.1.3 Data Frame / Remote Frame Figure 16-1: Data Frame R D 1 (11 + 1) (29 + 3) Data frame 6 0 ... 64 16 2 7 3 ( Y ) Q R S T U V W XY ( )( End of frame ACK field CRC field Data field Control field Arbitration field Start of frame ) Bus idle Interframe space Figure 16-2: Remote frame Remote Frame R D ( Y ) Q R S U VW XY ( )( ) Bus idle Interframe space End of frame ACK field CRC field Control field Arbitration field Start of frame Remark: This frame is transmitted when the reception node requests transmission. Data field is not transmitted even if the data length code '0' in the control field. User's Manual U16504EE1V1UD00 241 Chapter 16 16.1.4 Description of each field (1) CAN Controller "R" indicates recessive level. "D" indicates dominant level. Start of frame: The start of data frame and remote frame are indicated. Figure 16-3: Data Frame Interframe space on bus idle R D Start of frame Arbitration field 1 bit * The start of frame (SOF) is denoted by the falling edge of the bus signal. * Reception continues when 'Dominant level' is detected at the sample point. * The bus becomes idle state when 'Recessive level' is detected at a sample point. (2) Arbitration field: Sets priority, specifies data frame or remote frame, and defines the protocol mode. Figure 16-4: Arbitration Field/Standard Format Mode Arbitration field R D Control field Identifier ID28 . . . ID18 (11 bits) RTR IDE r0 (1 bit) (1 bit) 242 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-5: Arbitration Field/Extended Format Mode Arbitration field R D Control field Identifier ID28 . . . ID18 (11 bits) SRR IDE (1 bit) (1 bit) Identifier ID17 . . . ID0 (18 bits) RTR r1 (1 bit) r0 * ID28 - ID0 is the identifier. * The identifier is transmitted with MSB at first position. * Substitute Remote Request (SRR) is only used in extended format mode and is always recessive. Table 16-2: Bit Number of the Identifier Number 11 bits 29 bits Protocol Mode Identifier Standard format mode Extended format mode Table 16-3: Frame Type Data frame Remote frame RTR Setting RTR Bit 0 1 Table 16-4: Protocol Mode Standard format mode Extended format mode Mode Setting IDE Bit 0 1 User's Manual U16504EE1V1UD00 243 Chapter 16 (3) CAN Controller Control field: The data byte number DLC in the data field specifies the number of data bytes in the current frame (DLC=0 to 8). Figure 16-6: Control Field (Standard Format Mode) Arbitration field R D RTR IDE r0 Control field Data field DLC3 DLC2DLC1DLC0 Figure 16-7: Control Field (Extended Format Mode) Arbitration field R D RTR r1 r0 Control field Data field DLC3 DLC2DLC1DLC0 * The bits r0 and r1 are reserved bits for future use and are recommended to be recessive. Table 16-5: Data Length Code Setting Data Length Code DLC3 0 0 . . 0 1 DLC2 0 0 . . 1 X DLC1 0 0 . . 1 X DLC0 0 1 . . 1 X 7 8 Number of Data Bytes 0 1 Remark: In case of a remote frame, the data field is not generated even if data length code '0'. 244 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller (4) Data field: This field carries the data bytes to be sent. The number of data bytes is defined by the DLC value. Figure 16-8: Data Field Control field R D Data (8 bits) Data field CRC field Data (8 bits) (5) CRC field: This field consists of a 15-bit CRC sequence to check the transmission error and a CRC delimiter. Figure 16-9: CRC Field Data field and control field R D CRC field ACK field CRC sequence CRC delimiter (1 bit) (15 bits) * 15 bits CRC generation polynomial is expressed by P(X) = X 15 + X 14 + X 10 + X 8 + X 7 + X 4 + X 3 + 1. * Transmission node: Transmits the CRC sequence calculated from the start of frame, arbitration field, control field and data field eliminating stuff bits. * Reception node: The CRC received will be compared with the CRC calculated in the receiving node. For this calculation the stuff bits of the received CRC are eliminated. In case these do not match, the node issues an error frame. User's Manual U16504EE1V1UD00 245 Chapter 16 (6) ACK field: For check of normal reception. CAN Controller Figure 16-10: ACK Field CRC field R D ACK field End of frame ACK slot ACK delimiter (1 bit) (1 bit) * Receive node sets the ACK slot to dominant level if no error was detected. (7) End of frame: Indicates the end of the transmission/reception. Figure 16-11: End of Frame ACK field R D End of frame Interframe space of overload frame (7 bits) 246 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller (8) Interframe space: This sequence is inserted after data frames, remote frames, error frames, and overload frames in the serial bitstream on the bus to indicate start or end of a frame. The length of the interframe space depends on the error state (active or passive) of the node. (a) Error active: Consists of 3 bits intermission and bus idle. Figure 16-12: Interframe Space/Error Active Any frame R D Interframe space Any frame Intermission (3 bits) Bus idle (0 to bits) (b) Error passive: Consists of 3 bits intermission, suspend transmission and bus idle. Figure 16-13: Interframe Space/Error Passive Each frame R D Intermission (3 bits) Interframe space Each frame Suspend transmission (8 bits) Bus idle (0 to bits) Remark: The nominal value of the intermission field is 3 bits. However, transmission nodes may start immediately a transmission already in the 3rd bit of this field when a dominant level is detected. Table 16-6: Error State Error active Error passive Operation in the Error State Operation Any node in this state is able to start a transmission whenever the bus is idle. Any node in this state has to wait for 11 consecutive recessive bits before initiating a transmission. User's Manual U16504EE1V1UD00 247 Chapter 16 16.1.5 Error Frame CAN Controller * This frame is sent from a node if an error is detected. * The type of an Error Frame is defined by its error flag: ACTIVE ERROR FLAG or PASSIVE ERROR FLAG. Which kind of flag a node transmits after detecting an error condition depends on the internal count of the error counters of each node. Figure 16-14: Error frame Error Frame R D ( T ) Q R S ( U ) Interframe space or overload frame Error delimiter Error flag Error flag Error bit Table 16-7: No. 1 2 Name Error flag Error flag superpositioning Error delimiter Bit Number 6 0 to 6 Definition of each Field Definition Error active node: sends 6 bits dominant level continuously. Error passive node: sends 6 bits recessive level continuously. Nodes receiving an "error flag" detect bit stuff errors and issue error flags' themselves. Sends 8 bits recessive level continuously. In case of monitoring dominant level at 8th bit, an overload frame is transmitted after the next bit. An error frame is transmitted continuously after the bit where the error has occurred (in case of a CRC error, transmission continues after the ACK delimiter). Interframe space or overload frame continues. 3 8 4 Erroneous bit Interframe space/ overload frame 3/14 20 MAX 5 248 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.1.6 Overload Frame * This frame is started at the first bit of the intermission when the reception node is busy with exploiting the receive operation and is not ready for further reception. * When a bit error is detected in the intermission, also an overload frame is sent following the next bit after the bit error detection. * Detecting a dominant bit during the 3rd bit of intermission will be interpreted as START OF FRAME. * At most two OVERLOAD FRAMEs may be generated to delay the next DATA FRAME or REMOTE FRAME. Figure 16-15: Overload frame Overload Frame R D ( T ) Q R S ( U ) Interframe space or overload frame Overload delimiter Overload flag superpositioning (Node n) Overload flag (Node m) Each frame Table 16-8: No. 1 2 Name Overload flag Overload flag from any node Overload delimiter Any frame Interframe space/ overload frame Bit Number 6 0 to 6 Definition of each Frame Definition Sent 6 bits dominant level continuously. A node that receives an overload flag in the interframe space. Issues an overload flag. Sends 8 bits recessive level continuously. In case of monitoring dominant level at 8th bit, an overload frame is transmitted after the next bit. Output following the end of frame, error delimiter and overload delimiter. Interframe space or overload frame continues. 3 8 4 5 3/14 20 MAX User's Manual U16504EE1V1UD00 249 Chapter 16 CAN Controller 16.2 Function 16.2.1 Arbitration If two or more nodes happen to start transmission in coincidence, the access conflict is solved by a bitwise arbitration mechanism during transmission of the ARBITRATION FIELD. (1) When a node starts transmission: * During bus idle, the node having the output data can transmit. (2) When more than one node starts transmission: * The node with the lower identifier wins the arbitration. * Any transmitting node compares its output arbitration field and the data level on the bus. * It looses arbitration, when it sends recessive level and reads dominant from bus. Table 16-9: Level Detection Conformity of Level Non-conformity of Level Continuous Transmission Arbitration Status of Arbitrating Node The data output is stopped from the next bit and reception operation starts. (3) Priority of data frame and remote frame: * When a data frame and remote frame with the same message identifier are on the bus, the data frame has priority because its RTR bit carries 'Dominant level'. The data frame wins the arbitration. 16.2.2 Bit Stuffing When the same level continues for more than 5 bits, bit stuffing (insert 1 bit with inverse level) takes place. * Due to this a resynchronization of the bit timing can be done at least every 10 bits. * Nodes detecting an error condition send an error frame, violating the bit stuff rule and indicating this message to be erroneous for all nodes. Table 16-10: Bit Stuffing Transmission During the transmission of a data frame and a remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, 1 bit level with reverse level of data is inserted before the following bit. During the reception of a data frame and a remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, the reception is continued by deleting the next bit. Reception 250 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.2.3 Multi Master As the bus priority is determined by the identifier, any node can be the bus master. 16.2.4 Multi Cast Any message can be received by any node (broadcast). 16.2.5 Sleep Mode/Stop Function This is a function to put the CAN controller in waiting mode to achieve low power consumption. The SLEEP mode of the DCAN complies to the method described in ISO 11898. Additional to this SLEEP mode, which can be woken up by bus activities, the STOP mode is fully controlled by the CPU device. User's Manual U16504EE1V1UD00 251 Chapter 16 16.2.6 Error Control Function (1) Error types CAN Controller Table 16-11: Description of Error Type Detection Method Comparison of output level and level on the bus (except stuff bit) Check of the reception data at the stuff bit Comparison of the CRC generated from the reception data and the received CRC sequence Detection Condition Disagreement of both levels 6 consecutive bits of the same output level Disagreement of CRC Error Types Detection State Transmission/ Reception Transmission/ reception node Field/Frame Bit that output data on the bus at the start of frame to the end of frame, error frame and overload frame. Bit error Stuff error Transmission/ reception node Start of frame to CRC sequence CRC error Reception node Start of frame to data field Form error Field/frame check of the fixed format Detection of the fixed format error Detection of recessive level in ACK slot CRC delimiter ACK field Reception node End of frame Error frame Overload frame Transmission node ACK error Check of the ACK slot by the transmission node ACK slot (2) Output timing of the error frame Table 16-12: Type Bit error, stuff error, form error, ACK error Error passive Output Timing of the Error Frame Output timing Error frame is started at the next bit timing following the detected error CRC error Error frame is started at the next bit timing following the ACK delimiter (3) Measures when error occurs * Transmission node re-transmits the data frame or the remote frame after the error frame. * The CAN standard (ISO-11898) allows a programmable suppression of this re-transmission. It is called single shot mode. 252 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller (4) Error state (a) Types of error state * Three types of error state: These are error active, error passive and bus off. * The transmission error counter (TEC) and the reception error counter (REC) control the error state. * The error counters are incremented on each error occurrence (refer to Table 3-6). * If the value of error counter exceeds 96, warning level for error passive state is reached. * When only one node is active at start-up, it may not receive an acknowledgment on a transmitted message. This will increment TEC until error passive state is reached. The bus off state will not be reached because for this specific condition TEC will not increment any more if values greater than 127 are reached. * A node in bus off state will not issue any dominant level on the CAN transmit pin. The reception of messages is not affected by the bus off state. Table 16-13: Type Error active Error passive Operation Transmission/ reception Transmission Reception Transmission Reception Types of Error Output Error Flag Type Active error flag (6 bits of dominant level continue) Passive error flag (6 bits of recessive level continue) Communication cannot be made Does not exist Value of Error Counter 0 to 127 128 to 255 128 or more more than 255 - Bus off User's Manual U16504EE1V1UD00 253 Chapter 16 (b) Error counter CAN Controller * Error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counters are updated during the first bit of an error flag. Table 16-14: State Error Counter Transmission Error Counter (TEC) No change No change Reception Error Counter (REC) +1 +8 Reception node detects an error (except bit error in the active error flag or overload flag). Reception node detects dominant level following the error flag of the own error frame. Transmission node transmits an error flag. Exception: 1. ACK error is detected in the error passive state and dominant level is not detected in the passive error flag sent. 2. Stuff error generation in arbitration field. Bit error detection during active error flag and overload flag when transmitting node is in error active state. Bit error detection during active error flag and overload flag when receiving node is in error active state. When the node detects fourteen continuous dominant bits counted from the beginning of the active error flag or the overload flag, and every time, eight subsequent dominant bits after that are detected. Every time when the node detects eight continuous dominant bits after the passive error flag. When the transmitting node has completed to sent without error. When the reception node has completed to receive without error. +8 No change +8 No change No change +8 +8 +8 -1 (-0 when error counter = 0) No change No change -1 (1 REC 127) -0 (REC = 0) 119-127 (REC > 127) (c) Overload frame * In case the recessive level of first intermission bit is driven to dominant level, an overload frame occurs on the bus. Upon detection of an overload frame any transmit request will be postponed until the bus becomes idle. 254 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.2.7 Baud Rate Control Function (1) Nominal bit time (8 to 25 time quanta) * Definition of 1 data bit time is as follows. Figure 16-16: Nominal Bit Time (8 to 25 Time Quanta) Nominal bit time Sync segment Prop segment Phase segment 1 Phase segment 2 SJW Sample point SJW [1 Minimum time for one time/quantum (TQ) = 1/fx] * Sync segment: In this segment the bit synchronization is performed. * Prop segment: This segment absorbs delays of the output buffer, the CAN bus and the input buffer. Prop segment time =(output buffer delay) + (CAN bus delay) + (input buffer delay). * Phase segment 1/2: These segments compensate the data bit time error. The larger the size measured in TQ is, the larger is the tolerable error. * The synchronization jump width (SJW) specifies the synchronization range. The SJW is programmable. SJW can have less or equal number of TQ as phase segment 2. Table 16-15: Segment Name and Segment Length Segment Length (allowed Number of TQs) 1 Programmable 1 to 8 Programmable 1 to 8 Maximum of phase segment 1 and the IPT Note Programmable 1 to 4 Segment Name Sync segment (Synchronization segment) Prop segment (Propagation segment) Phase segment 1 (Phase buffer segment 1) Phase segment 2 (Phase buffer segment 2) SJW Note: IPT = Information Processing Time. It needs to be less than or equal to 2 TQ. User's Manual U16504EE1V1UD00 255 Chapter 16 (2) Adjusting synchronization of the data bit CAN Controller * The transmission node transmits data synchronized to the transmission node bit timing. * The reception node adjusts synchronization at recessive to dominant edges on the bus. Depending on the protocol this synchronization can be a hard or soft synchronization. (a) Hard synchronization This type of synchronization is performed when the reception node detects a start of frame in the bus idle state. * When the node detects a falling edge of a SOF, the current time quanta becomes the synchronization segment. The length of the following segments are defined by the values programmed into the SYNC0 and SYNC1 registers. Figure 16-17: Bus idle CAN bus Adjusting Synchronization of the Data Bit Start of frame Bit timing Sync segment Prop segment Phase segment 1 Phase segment 2 256 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller (b) Soft synchronization When a recessive to dominant level change on the bus is detected, a soft synchronization is performed. * If the phase error is larger than the programmed SJW value, the node will adjust the timing by applying this SJW-value. Full synchronization is achieved by subsequent adjustments on the next recessive to dominant edge(s). * These errors that are equal or less of the programmed SJW are corrected instantly and full synchronization is achieved already for the next bit. * The TQ at which the edge occurs becomes sync segment forcibly, if the phase error is less than or equal to SJW. Figure 16-18: Bit Synchronization Phase segment Sync segment -SJW Prop segment Phase segment 2 +SJW Sync segment Prop segment User's Manual U16504EE1V1UD00 257 Chapter 16 16.2.8 State Shift Chart Figure 16-19: Reception CAN Controller Transmission State Shift Chart C Start of frame End Bit error Arbitration field A Reception RTR = 1 Control field RTR = 0 Data field End CRC field End ACK field End End of frame End Intermission 1 Error passive Error active Bit error End Bit error End Error frame Bit error Form error ACK error Bit error Bit error Bit error Overload frame Intermission 2 8 bits of '1' Initialization setting Start of frame reception Bus idle B Reception Start of frame transmission 258 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-20: Transmission Reception State Shift Chart B Start of frame Transmission End Arbitration field Stuff error A RTR = 1 Control field RTR = 0 Data field End CRC field End ACK field End End of frame End Intermission 1 Stuff error Stuff error CRC error, stuff error ACK error, bit error Bit error, form error End Not ready Bit error End Not ready Error frame Form error Overload frame Initialization setting Start of frame transmission Bus idle C Transmission Start of frame reception User's Manual U16504EE1V1UD00 259 Chapter 16 Figure 16-21: CAN Controller Error State Shift Chart (a) Transmission Error active TEC > 128 TEC < 127 Error passive TEC Bus off TEC = 0 > 256 TEC = Transmission error counter (b) Reception Error active REC > 128 Error passive REC < 127 REC = Reception error counter 260 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.3 Outline Description Figure 16-22: Structural Block Diagram CANL CANH CPU Access Receive Messages Receive Messages Receive Messages Receive Messages Bus Arbitration Logic CPU SFR Memory Access Engine Memory Buffer RAM Interface Management High Speed RAM (includes global registers) Transmit Buffers Transmit Buffers CAN Protocol Time Stamp Signal Timer DCAN-Interface External Transceiver This interface part handles all protocol activities by hardware in the CAN protocol part. The memory access engine fetches information for the CAN protocol transmission from the dedicated RAM area to the CAN protocol part or compares and sorts incoming information and stores it into predefined RAM areas. The DCAN interfaces directly to the RAM area that is accessible by the DCAN and by the CPU. The DCAN part works with an external bus transceiver which converts the transmit data and receive data lines to the electrical characteristics of the CAN bus itself. User's Manual U16504EE1V1UD00 261 Chapter 16 CAN Controller 16.4 Connection with Target System The DCAN Macro has to be connected to the CAN bus with an external transceiver. Figure 16-23: Connection to the CAN Bus CTXD DCAN Macro CRXD Transceiver CANL CANH 16.5 CAN Controller Configuration The CAN-module consists of the following hardware . Table 16-16: CAN Configuration Item Message definition CAN input/output In RAM area 1 (CTXD) 1 (CRXD) CAN control register (CANC) Transmit control register (TCR) Receive message register (RMES) Redefinition control register (REDEF) CAN error status register (CANES) Transmit error counter (TEC) Receive error counter (REC) Message count register (MCNT) Bit rate prescaler (BRPRS) Synchronous control register 0 (SNYC0) Synchronous control register 1 (SYNC1) Mask control register (MASKC) Configuration Control registers 262 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.6 Special Function Register for CAN-module Table 16-17: Register Name CAN control register Transmit control register Receive message register Redefinition control register CAN error status register Transmit error counter Receive error counter Message count register Bit rate prescaler Synchronous control register 0 Synchronous control register 1 Mask control register Symbol CANC TCR RMES REDEF CANES TEC REC MCNT BRPRS SYNC0 SYNC1 MASKC SFR Definitions R/W R/W R/W R R/W R/W R R R R/W R/W R/W R/W Bit Manipulation Units 1-bit x x 8-bit x x x x x x x x x x x x 16-bit After Reset 01H 00H 00H 00H 00H 00H 00H C0H 00H 18H 0EH 00H The following SFR bits can be accessed with 1-bit instructions. The other SFR registers have to be accessed with 8-bit instructions. Table 16-18: SFR Bit Definitions Name SOFE SLEEP INIT DEF Description Start of frame enable Sleep mode Initialize Redefinition enable Bit CANC.4 CANC.2 CANC.0 REDEF.7 User's Manual U16504EE1V1UD00 263 Chapter 16 CAN Controller 16.7 Message and Buffer Configuration Table 16-19: Address Note 2 00xH 01xH 02xH 03xH 04xH 05xH 06xH 07xH 08xH 09xH 0AxH 0BxH 0CxH 0DxH 0ExH 0FxH 10xH 11xH Message and Buffer Configuration Register Name R/W After Reset Transmit buffer 0 Transmit buffer 1 Receive message 0 / Mask 0 Receive message 1 Receive message 2 / Mask 1 Receive message 3 Receive message 4 Receive message 5 Receive message 6 Receive message 7 Receive message 8 Receive message 9 Receive message 10 Receive message 11 Receive message 12 Receive message 13 Receive message 14 Receive message 15 R/W Note 1 Notes: 1. Contents is undefined, because data resides in normal RAM area. 2. This address is an offset to the RAM area starting address defined with CADD0/1 in the message count register (MCNT). 264 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.8 Transmit Buffer Structure The DCAN has two independent transmit buffers. The two buffers have a 16 byte data structure for standard and extended frames with the ability to send up to 8 data bytes per message. The structure of the transmit buffer is similar to the structure of the receive buffers. The CPU can use addresses that are specified as "unused" in the transmit buffer layout. As well the CPU may use unused ID addresses, unused data addressesNote, and an unused transmit buffer of the DCAN for its own purposes. The control bits, the identification and the message data have to be stored in the message RAM area. The transmission control is done by the TCR register. A transmission priority selection allows the customer to realize an application specific priority selection. After the priority selection the transmission can be started by setting the TXRQn bit (n = 0, 1). In the case that both transmit buffers are used, the transmit priorities can be set. For this purpose the DCAN has the TXP bit in the TCR register. The application software has to set this priority before the transmission is started. The two transmit buffers supply two independent interrupt lines for an interrupt controller. Note: Message objects that need less than 8 data byte (DLC < 8) may use the remaining bytes (8 - DLC) for application purposes. 16.9 Transmit Message Format Table 16-20: Name TCON AddressNote n0H n1H IDTX0 IDTX1 IDTX2 IDTX3 IDTX4 n2H n3H n4H n5H n6H n7H DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 n8H n9H nAH nBH nCH nDH nEH nFH ID extended part Bit 7 IDE Bit 6 RTR Transmit Message Format Bit 5 0 Bit 4 0 Bit 3 DLC3 Bit 2 DLC2 Bit 1 DLC1 Bit 0 DLC0 Unused ID standard part ID standard part 0 0 0 0 0 ID extended part ID extended part 0 0 Unused Message data byte 0 Message data byte 1 Message data byte 2 Message data byte 3 Message data byte 4 Message data byte 5 Message data byte 6 Message data byte 7 0 0 0 0 Note: This address is a relative offset to the starting address of the transmit buffer. User's Manual U16504EE1V1UD00 265 Chapter 16 (1) Transmit Message Definition CAN Controller The memory location labelled TCON includes the information of the RTR bit and the bits of the control field of a data or remote frame. TCON is set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets TCON to an undefined value. Figure 16-24: Symbol TCON 7 IDE 6 RTR 5 0 4 0 Transmit Message Definition Bits 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Address After Reset R/W xxx0H undefined R/W IDE 0 1 RTR 0 1 Identifier Extension Select Transmit standard frame message; 11 bit identifier Transmit extended frame message; 29 bit identifier Remote Transmission Select Transmit data frames Transmit remote frames Data Length Code Selection of Transmit Message 0 data bytes 1 data bytes 2 data bytes 3 data bytes 4 data bytes 5 data bytes 6 data bytes 7 data bytes 8 data bytes Note DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Others than above Remark: The control field describes the format of frame that is generated and its length. The reserved bits of the CAN protocol are always sent in dominant state (0). Note: The data length code selects the number of bytes which have to be transmitted. Valid entries for the data length code (DLC) are 0 to 8. If a value greater than 8 is selected, 8 bytes are transmitted in the data frame. The Data Length Code is specified in DLC3 through DLC0. 266 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller (2) Transmit Identifier Definition These memory locations set the message identifier in the arbitration field of the CAN protocol. IDTX0 to IDTX4 register can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets IDTX0 to IDTX4 to an undefined value. Figure 16-25: Symbol IDTX0 IDTX1 IDTX2 IDTX3 IDTX4 7 ID28 ID20 ID17 ID9 ID1 6 ID27 ID19 ID16 ID8 ID0 5 ID26 ID18 ID15 ID7 0 4 ID25 0 ID14 ID6 0 3 ID24 0 ID13 ID5 0 Transmit Identifier 2 ID23 0 ID12 ID4 0 1 ID22 0 ID11 ID3 0 0 ID21 0 ID10 ID2 0 Address After Reset R/W xxx2H xxx3H xxx4H xxx5H xxx6H undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W Remark: If a standard frame is defined by the IDE bit in the TCON byte then IDTX0 and IDTX1 are used only. IDTX2 to IDTX4 are free for use by the CPU for application needs. User's Manual U16504EE1V1UD00 267 Chapter 16 (3) Transmit Data Definition CAN Controller These memory locations set the transmit message data of the data field in the CAN frame. DATA0 to DATA7 can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets DATA0 to DATA7 to an undefined value. Figure 16-26: Symbol DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 7 6 5 4 3 Transmit Data 2 1 0 Address After Reset R/W xxx8H xxx9H xxxAH xxxBH xxxCH xxxDH xxxEH xxxFH undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W Remark: Unused data bytes that are not used by the definition in the DLC bits in the TCON byte are free for use by the CPU for application needs. 268 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.10 Receive Buffer Structure The DCAN has up to 16 receive buffers. The number of used buffers is defined by the MCNT register. Unused receive buffers can be used as application RAM for the CPU. The received data is stored directly in this RAM area. The 16 buffers have a 16 byte data structure for standard and extended frames with a capacity of up to 8 data bytes per message. The structure of the receive buffer is similar to the structure of the transmit buffers. The semaphore bits DN and MUC enable a secure reception detection and data handling. For the first 8 receive message buffers the successful reception is mirrored by the DN-flags in the RMES register. The receive interrupt request can be enabled or disabled for each used buffer separately. User's Manual U16504EE1V1UD00 269 Chapter 16 CAN Controller 16.11 Receive Message Format Table 16-21: Name IDCON DSTAT IDREC0 IDREC1 IDREC2 IDREC3 IDREC4 AddressNote 1 n0H n1H n2H n3H n4H n5H n6H n7H DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 n8H n9H nAH nBH nCH nDH nEH nFH Bit 7 0 DN Receive Message Format Bit 5 0 R1 Bit 4 0 R0 ID standard part Bit 3 0 Bit 2 ENI Bit 1 RTR DLC Bit 0 IDE Bit 6 0 MUC ID standard part 0 0 0 0 RTRRECNote 2 ID extended part ID extended part ID extended part 0 0 0 unused Message data byte 0 Message data byte 1 Message data byte 2 Message data byte 3 Message data byte 4 Message data byte 5 Message data byte 6 Message data byte 7 0 0 0 Notes: 1. This address is a relative offset to the start address of the receive buffer. 2. RTRREC is the received value of the RTR message bit when this buffer is used together with a mask function. By using the mask function a successfully received identifier overwrites the bytes IDREC0 and IDREC1 for standard frame format and IDREC0 to IDREC4 for extended frame format. For the RTRREC bit exist two modes: * RTR bit in the MCON byte of the dedicated mask is set to 0. In this case RTRREC will always be written to 0 together with the update of the IDn bits in IDREC1. The received frame type (data or remote) is defined by the RTR bit in IDCON of the buffer. RTR bit in the MCON byte of the dedicated mask is set to 1 (data and remote frames are accepted). In this case the RTR bit in IDCON has no meaning. The received message type passed the mask is shown in RTRREC. * If a buffer is not assigned to a mask function (mask 1, mask 2 or global mask) the bytes IDREC0 to IDREC4 are only read for comparing. During initialization the RTRREC should be defined to 0. 270 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller (1) Receive control bits definition The memory location labelled IDCON defines the kind of frame (data or remote frame with standard or extended format) that is monitored for the associated buffer. Notification by the receive interrupt upon successful reception can be selected for each receive buffer separately. IDCON can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets IDCON to an undefined value. Figure 16-27: Symbol IDCON 7 0 6 0 5 0 4 0 Control bits for Receive Identifier 3 0 2 ENI 1 RTR 0 IDE Address After Reset R/W xxx0H undefined R/W IDE 0 1 Identifier Extension Select Receive standard frame message; 11-bit identifier Receive extended frame message; 29-bit identifier RTR 0 1 Remote Transmission Select Receive data frames Receive remote frames ENI 0 1 Enable Interrupt on ReceiveNote No interrupt generated Generate receive interrupt after reception of valid message The control bits define the type of message that is transferred in the associated buffer if this type of message appears on the bus. This byte will never be written by the DCAN. Only the host CPU can change this byte. Note: The user has to define with the ENI bit if he wants to set a receive interrupt request when new data is received in this buffer. User's Manual U16504EE1V1UD00 271 Chapter 16 (2) Receive status bits definition CAN Controller The memory location labelled DSTAT sets the receive status bits of the arbitration field of the CAN protocol. DSTAT can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets DSTAT to an undefined value. Figure 16-28: Symbol DSTAT 7 DN 6 MUC 5 R1 4 R0 Receive Status Bits (1/2) 3 2 DLC2 1 DLC1 0 DLC0 Address After Reset R/W xxx1H undefined R/W DLC3 The receive status reflects the current status of a message. It signals whether new data is stored or if the DCAN currently transfers data into this buffer. In addition the data length of the last transferred data and the reserved bits of the protocol are shown. DN 0 1 No change in data Data changed Data New The DCAN-module sets DN twice. At first when it starts storing a message from the shadow buffer into the receive buffer and secondly when it finished the operation. The CPU needs to clear this bit, to signal by itself that it has read the data. During initialization of the receive buffers the DN-bit should also be cleared. Otherwise the CPU gets no information on an update of the buffer after a successful reception. MUC 0 1 Memory Update CAN does not access data part CAN is transferring new data to message buffer The DCAN-module sets MUC when it starts transferring a message into the buffer and clears the MUC bit when the transfer is finished. R1 0 1 Reserved Bit 1 Reserved bit 1 of received message was "0" Reserved bit 1 of received message was "1" R0 0 1 Reserved Bit 0 Reserved bit 0 of received message was "0" Reserved bit 0 of received message was "1" 272 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-28: Receive Status Bits (2/2) DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Length Code Selection of Receive Message 0 data bytes 1 data bytes 2 data bytes 3 data bytes 4 data bytes 5 data bytes 6 data bytes 7 data bytes 8 data bytes Note Others than above DSTAT is written by the DCAN two times during message storage: At the first access to this buffer DN = 1, MUC = 1, reserved bits and DLC are written. At the last access to this buffer DN = 1, MUC = 0, reserved bits and DLC are written. Note: Valid entries for the data length code are 0 to 8. If a value higher than 8 is received, 8 bytes are stored in the message buffer frame together with the data length code received in the DLC of the message. User's Manual U16504EE1V1UD00 273 Chapter 16 (3) Receive Identifier Definition CAN Controller These memory locations define the receive identifier of the arbitration field of the CAN protocol. IDREC0 to IDREC4 can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets IDREC0 to IDREC4 to an undefined value. Figure 16-29: Symbol IDREC0 IDREC1 IDREC2 IDREC3 IDREC4 7 ID28 ID20 ID17 ID9 ID1 6 ID27 ID19 ID16 ID8 ID0 5 ID26 ID18 ID15 ID7 0 4 ID25 0 ID14 ID6 0 3 ID24 0 ID13 ID5 0 Receive Identifier 2 ID23 0 ID12 ID4 0 1 ID22 0 ID11 ID3 0 0 ID21 RTRREC ID10 ID2 0 Address After Reset R/W xxx2H xxx3H xxx4H xxx5H xxx6H undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W The identifier of the receive message has to be defined during the initialization of the DCAN. The DCAN uses this data for the comparison with the identifiers received on the CAN bus. For normal message buffers without mask function this data is only read by the DCAN for comparison. In combination with a mask function this data is overwritten by the received ID that has passed the mask. The identifier of the receive messages should not be changed without being in the initialization phase or setting the receive buffer to redefinition in the RDEF register, because the change of the contents can happen at the same time when the DCAN uses the data for comparison. This can cause inconsistent data stored in this buffer and also the ID-part can be falsified in case of using mask function. Remarks: 1. The unused parts of the identifier (IDREC1 bit 4 - 0 always and IDREC4 bit 5 - 0 in case of extended frame reception) may be written by the DCAN to "0". They are not released for other use by the CPU. 2. RTRREC is the received value of the RTR message bit when this buffer is used together with a mask function. By using the mask function a successfully received identifier overwrites the IDREC0 and IDREC1 registers for standard frame format and the IDREC0 to IDREC4 registers for extended frame format. For the RTRREC bit exists two modes: * RTR bit in the MCON register of the dedicated mask is set to "0". In this case RTRREC bit will always be written to "0" together with the update of the IDn bits (n = 18 to 20) in IDREC1. The received frame type (data or remote) is defined by the RTR bit in IDCON of the buffer. RTR bit in the MCON register of the dedicated mask is set to "1" (data and remote frames are accepted). In this case the RTR bit in IDCON register has no meaning. The received message type passed the mask is shown in RTRREC bit. * If a buffer is not dedicated to a mask function (mask 1, mask 2 or global mask) the IDREC0 to IDREC4 registers are only read for comparing. All receive identifiers should be defined to "0" before the application sets up its specific values. 274 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller (4) Receive Message Data Part These memory locations set the receive message data part of the CAN protocol. DATA0 to DATA7 can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets DATA0 to DATA7 to an undefined value. Figure 16-30: Symbol DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 7 6 5 4 3 Receive Data 2 1 0 Address After Reset R/W xxx8H xxx9H xxxAH xxxBH xxxCH xxxDH xxxEH xxxFH undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W The DCAN stores received data bytes in this memory area. Only those data bytes which are actually received and match with the identifier are stored in the receive buffer memory area. If the DLC is less than eight, the DCAN will not write additional bytes exceeding the DLC value up to eight. The DCAN stores a maximum of 8 bytes (according to the CAN protocol rules) even when the received DLC is greater than eight. User's Manual U16504EE1V1UD00 275 Chapter 16 CAN Controller 16.12 Mask Function Table 16-22: Mask Function Name MCON Address n0H n1H MREC0 MREC1 MREC2 MREC3 MREC4 n2H n3H n4H n5H n6H n7H n8H n9H nAH nBH nCH nDH nEH nFH ID extended part 0 ID standard part Unused ID standard part 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RTR Bit 0 ID extended part ID extended part 0 Unused Unused Unused Unused Unused Unused Unused Unused Unused 0 0 0 0 Receive message buffer 0 and buffer 2 can be switched for masked operation with the mask control register (MASKC). In this case the message does not hold message identifier and data of the frame. Instead, it holds identifier and RTR mask information for masked compare operations for the next higher message buffer number. In case the global mask is selected, it keeps mask information for all higher message buffer numbers. A mask does not store any information about identifier length. Therefore the same mask can be used for both types of frames (standard and extended) during global mask operation. All unused bytes can be used by the CPU for application needs. (1) Identifier Compare with Mask The identifier compare with mask provides the possibility to exclude some bits from the comparison process. That means each bit is ignored when the corresponding bit in the mask definition is set to one. The setup of the mask control register (MASKC) defines which receive buffer is used as a mask and which receive buffer uses which mask for comparison. The mask does not include any information about the identifier type to be masked. This has to be defined within the dedicated receive buffer. Therefore a global mask can serve for standard receive buffers at the same time as for extended receive buffer. 276 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-31: Identifier Compare with Mask Received Identifier Compare Bit by Bit Store on equal Mask stored in Receive Buffer 0 or 2 Disable Compare for masked Bits Identifier stored in Receive Buffer This function implements the so called basic-CAN behaviour. In this case the type of identifier is fixed to standard or extended by the setup of the IDE bit in the receive buffer. The comparison of the RTR bit can also be masked. It is possible to receive data and remote frames on the same masked receive buffer. The following information is stored in the receive buffer: * Identifier (11 or 29 bit as defined by IDE bit) * Remote bit (RTRREC) if both frames types (data or remote) can be received by this buffer * Reserved bits * Data length code (DLC) * Data bytes as defined by DLC Caution: All writes into the DCAN memory are byte accesses. Unused bits in the same byte will be written zero. Unused bytes will not be written and are free for application use by the CPU. User's Manual U16504EE1V1UD00 277 Chapter 16 (2) Mask Identifier Control Register (MCON) CAN Controller The memory location labelled MCON sets the mask identifier control bit of the CAN protocol. MCON can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets MCON to an undefined value. Figure 16-32: Symbol MCON 7 0 6 0 5 0 4 0 Control Bits for Mask Identifier 3 0 2 0 1 RTR 0 0 Address After Reset R/W xxx0H undefined R/W RTR 0 1 Remote Transmission Select Check RTR bit of received message Note 1 Receive message independent from RTR bit Note 2 Notes: 1. For RTR = 0 the received frame type (data or remote) is defined by the RTR bit in IDCON of the dedicated buffer. In this case RTRREC will always be written to "0" together with the update of the IDn bits (n = 18 to 20) in IDREC1. 2. In case RTR in MCON is set to "1", RTR bit in IDCON of the dedicated receive buffer has no meaning. The received message type passed the mask is shown in the RTRREC bit. 278 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller (3) Mask Identifier Definition These memory locations set the mask identifier definition of the DCAN. MREC0 to MREC4 can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets MREC0 to MREC4 to an undefined value. Figure 16-33: Symbol MREC0 MREC1 MREC2 MREC3 MREC4 7 MID28 MID20 MID17 MID9 MID1 6 MID27 MID19 MID16 MID8 MID0 5 MID26 MID18 MID15 MID7 0 4 MID25 0 MID14 MID6 0 3 MID24 0 MID13 MID5 0 Mask Identifier 2 MID23 0 MID12 MID4 0 1 MID22 0 MID11 MID3 0 0 MID21 0 MID10 MID2 0 Address After Reset R/W xxx2H xxx3H xxx4H xxx5H xxx6H undefined R/W undefined R/W undefined R/W undefined R/W undefined R/W MIDn 0 1 Mask Identifier Bit (n = 0...28) Check IDn bit in IDREC0 through IDREC4 of received message Receive message independent from IDn bit User's Manual U16504EE1V1UD00 279 Chapter 16 CAN Controller 16.13 Operation of the CAN Controller 16.13.1 CAN control register (CANC) The operational modes are controlled via the CAN control register CANC. CANC can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets CANC to 01H. Figure 16-34: Symbol CANC 7 RXF R 6 TXF R 5 0 R <4> CAN Control Register (1/2) 3 <2> 1 STOP R/W <0> INIT R/W Address FFB0H After Reset 01H SOFE SOFSEL SLEEP R/W R/W R/W CANC.5 has always to be written as 0. INIT 0 1 Request status for operational modes Normal operation Initialization mode The INIT is the request bit to control the DCAN. INIT starts and stops the CAN protocol activities. Due to bus activities disabling the DCAN is not allowed any time. Therefore changing the INIT bit must not have an immediate effect to the CAN protocol activities. Setting the INIT bit is a request only. The INITSTAT bit in the CANES register reflects if the request has been granted. The registers MCNT, SYNC0, SYNC1, and MASKC are write protected while INIT is cleared independently of INITSTAT. Any write to these registers when INIT is set and the initialisation mode is not confirmed by the INITSTAT bit can have unexpected behaviour to the CAN bus. STOP 0 1 Stop Mode Selection Normal sleep operation / Sleep mode is released when a transition on the CAN bus is detected Stop operation / Sleep mode is cancelled only by CPU access. No wake up from CAN bus SLEEP 0 1 Sleep/Stop Request for CAN protocol Normal operation CAN protocol goes to sleep or stop mode depending on STOP bit 280 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-34: CAN Control Register (2/2) The clock supply to the DCAN is switched off during initialization, DCAN Sleep, and DCAN Stop mode. All modes are only accepted while CAN protocol is in idle state, whereby the CRXD pin must be recessive (= high level). A sleep or stop request out of idle state is rejected and the WAKE bit in CANES is set. DCAN Sleep and DCAN Stop mode can be requested in the same manner. The only difference is that the DCAN Stop mode prevents the wake up by CAN bus activity. Caution: The DCAN Sleep or DCAN Stop mode can not be requested as long as the WAKE bit in CANES is set. The DCAN Sleep mode is cancelled under following conditions: a) CPU clears the SLEEP bit. b) Any transition while idle state on CAN bus (STOP = 0). c) CPU sets SLEEP, but CAN protocol is active due to bus activity. The WAKE bit in CANES is set under condition b) and c). SOFSEL 0 1 Start of Frame Output Function Select Last bit of EOF is used to generate the time stamp SOF is used to generate the time stamp SOFE 0 1 Start of Frame Enable SOFOUT does not change SOFOUT toggles depending on the selected mode Figure 16-35: Last bit of EOF DCAN Support SOF Data CRC EOF FRC T Q MUX T-FF SOFOUT Capture Register Receive Buffer 4 SOFSEL SOFE Clear SOFC DCAN 16 Bit Timer The generation of an SOFOUT signal can be used for time measurements and for global time base synchronization of different CAN nodes as a prerequisite for time triggered communication. User's Manual U16504EE1V1UD00 281 Chapter 16 CAN Controller Table 16-23: SOFSEL x 0 1 SOFC x x 0 Possible Setup of the SOFOUT Function SOFE 0 1 1 SOFOUT Function Time stamp function disabled Toggles with each EOF Toggles with each start of frame on the CAN Bus Toggles with each start of frame on the CAN bus. Clears SOFE bit when DCAN starts to store a message in receive buffer 4 1 1 1 SOFC is located in the synchronization register SYNC1. RESET and setting of the INIT bit of CANC register clears the SOFOUT to 0. Table 16-24: TXF 0 1 No transmission Transmission / Reception Flag Transmission Flag Transmission active on CAN bus Note RXF 0 1 Reception Flag No data on the CAN bus Reception active on the CAN bus The TXF and RXF bits of CANC register show the present status of the DCAN to the bus. If both bits are cleared, the bus is in idle state. RXF and TXF bits are read-only bits. During initialization mode both bits do not reflect the bus status. Note: Transmission is active until intermission is completed. 282 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-36: INT Object n Valid message Other valid or invalid message Valid message Time Stamp Function INT Object n SOF SOF SOF Enable SOF Edge for capture Edge for capture Figure 16-37: Any valid or invalid message SOFOUT Toggle Function Any valid or invalid message Any valid or invalid message SOF SOF SOF Edge for capture Enable SOF Edge for capture Edge for capture Figure 16-38: Global Time System Function INT Object n Other valid or invalid message Valid sync. message buffer 4 Other valid or invalid message SOF SOF SOF Edge for capture Enable SOF Edge for capture Disable SOF User's Manual U16504EE1V1UD00 283 Chapter 16 16.13.2 DCAN Error Status Register This register shows the status of the DCAN. CAN Controller CANES has to be set with an 8-bit memory manipulation instruction. RESET input sets CANES to 00H. The RESET sets the INIT-bit in CANC register, therefore CANES will be read as 08H after RESET release. Figure 16-39: Symbol CANES 7 BOFF R 6 RECS R 5 TECS R 4 0 R CAN Error Status Register (1/3) 3 INITSTATE R 2 VALID R/W 1 WAKE R/W 0 OVER R/W Address FFB4H After Reset 00H Remark: Caution: BOFF, RECS, TECS and INITSTATE are read only bits. Don't use bit operations on this SFR. The VALID, WAKE and OVER bits have a special behavior during CPU write operations: * * Writing a "0" to them do not change them. Writing an "1" clears the associated bit. This avoids any timing conflicts between CPU access and internal activities. An internal set condition of a bit overrides a CPU clear request at the same time. BOFF 0 1 Bus Off Flag Transmission error counter 255 Transmission error counter > 255 BOFF is cleared after receiving 128 x 11 bits recessive state (Bus idle) or by issuing a hard DCAN reset with the TLRES bit in the MCNTn register Note. An interrupt is generated when the BOFF bit changes its value. RECS 0 1 Reception error counter status Reception error counter < 96 Reception error counter 96 / Warning level for error passive reached RECS is updated after each reception. An interrupt is generated when RECS changes its value. Note: Issuing TLRES bit may violate the minimum recovery time as defined in ISO-11898. 284 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-39: CAN Error Status Register (2/3) TECS 0 1 Transmission error counter status Transmission error counter < 96 Transmission error counter 96 / Warning level for error passive reached TECS is updated after each reception. An interrupt is generated when TECS changes its value. INITSTATE 0 1 Operational status of the DCAN CAN is in normal operation CAN is stopped and ready to accept new configuration data INITSTATE changes with a delay to the INIT bit in CANC register. The delay depends on the current bus activity and the time to set all internal activities to inactive state. This time can be several bit times long. While BOFF bit is set, a request to go into the initialization mode by setting the INIT bit is ignored. In this case the INITSTATE bit will not be set until the Bus-off state is left. VALID 0 1 Valid protocol activity detected No valid message detected by the CAN protocol Error free message reception from CAN bus This bit shows valid protocol activities independent from the message definitions and the RXONLY bit setting in SYNC1n register. VALID is updated after each reception. The VALID bit will be set at the end of the frame when a complete protocol without errors has been detected. Cautions: 1. The VALID bit is cleared if CPU writes an "1" to it, or when the INIT bit in CANC register is set. 2. Writing a "0" to the valid bit has no influence. User's Manual U16504EE1V1UD00 285 Chapter 16 Figure 16-39: CAN Controller CAN Error Status Register (3/3) WAKE 0 1 Normal operation Wake up Condition Sleep mode has been cancelled or sleep/stop mode request was not granted This bit is set and an error interrupt is generated under the following circumstances: a) A CAN bus activity occurs during DCAN Sleep mode. b) Any attempt to set the SLEEP bit in the CAN control register during receive or transmit operation will immediately set the WAKE bit. The CPU must clear this bit after recognition in order to receive further error interrupts, because the error interrupt line is kept active as long as this bit is set. Cautions: 1. The WAKE bit is cleared to "0" if CPU writes an "1" to it, or when the INIT bit in CANC register is set. 2. Writing a "0" to the WAKE bit has no influence. OVER 0 1 Normal operation Overrun Condition Overrun occurred during access to RAM The overrun condition is set whenever the CAN can not perform all RAM accesses that are necessary for comparing and storing received data or fetching transmitted data. Typically, the overrun condition is encountered when the frequency for the macro is too low compared to the programmed baud rate. An error interrupt is generated at the same time. The DCAN interface will work properly (i. e. no overrun condition will occur) with the following settings: The DCAN clock as defined with the PRM bits in the BRPRS register is set to a minimum of 16 times of the CAN baudrate and the selected CPU clock (defined in the PCC register) is set to a minimum of 16 times of the baudrate. Possible reasons for an overrun condition are: * Too many messages are defined. * DMA access to RAM area is too slow compared to the CAN Baudrate. The possible reactions of the DCAN differ depending on the situation, when the overrun occurs. 286 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Table 16-25: Overrun Situation Possible Reactions of the DCAN When detected DCAN Behavior Cannot get transmit data. The frame itself conforms to the CAN specification, but its content is faulty. Next data byte request from protocol. Corrupted data or ID in the frame. Immediate during the frame. TXRQx bit (x = 0, 1) is not cleared. DCAN will retransmit the correct frame after synchronization to the bus. Data storage is ongoing during the six bit of the next frame. Data in RAM is inconsistent. No receive flags. DN and MUC bit may be set in message. Cannot store receive data. Cannot get data for ID comparison ID compare is ongoing during six bits Message is not received and its data of next frame. is lost. 16.13.3 CAN Transmit Error Counter This register shows the transmit error counter. TEC register can be read with an 8-bit memory manipulation instruction. RESET input sets TEC to 00H. Figure 16-40: Symbol TEC 7 TEC7 R 6 TEC6 R 5 TEC5 R 4 TEC4 R Transmit Error Counter 3 TEC3 R 2 TEC2 R 1 TEC1 R 0 TEC0 R Address FFB5H After Reset 00H The transmit error counter reflects the status of the error counter for transmission errors as it is defined in the CAN protocol according ISO 11898. 16.13.4 CAN Receive Error Counter This register shows the receive error counter. REC can be read with an 8-bit memory manipulation instruction. RESET input sets REC to 00H. Figure 16-41: Symbol REC 7 REC7 R 6 REC6 R 5 REC5 R 4 REC4 R Receive Error Counter 3 REC3 R 2 REC2 R 1 REC1 R 0 REC0 R Address FFB6H After Reset 00H The receive error counter reflects the status of the error counter for reception errors as it is defined in the CAN protocol according ISO 11898. User's Manual U16504EE1V1UD00 287 Chapter 16 16.13.5 Message Count Register CAN Controller This register sets the number of receive message buffers and allocates the RAM area of the receive message buffers, which are handled by the DCAN-module. MCNT can be read with an 8-bit memory manipulation instruction. RESET input sets MCNT to C0H. Figure 16-42: Symbol 7 R/W 6 R/W 5 R/W Message Count Register (MCNT) (1/2) 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Address FFB7H After Reset C0H MCNT CADD1 CADD0 TLRES MCNT4 MCNT3 MCNT2 MCNT1 MCNT0 This register is readable at any time. Write is only permitted when the CAN is in initialization mode. MCNT4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 MCNT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 x MCNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 x MCNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 x MCNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 x Receive Message Count Setting prohibited 1 receive buffer 2 receive buffer 3 receive buffer 4 receive buffer 5 receive buffer 6 receive buffer 7 receive buffer 8 receive buffer 9 receive buffer 10 receive buffer 11 receive buffer 12 receive buffer 13 receive buffer 14 receive buffer 15 receive buffer 16 receive buffer Setting prohibited, will be automatically changed to 16 288 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-42: Message Count Register (MCNT) (2/2) TLRES 0 1 Reset function for CAN Protocol Machine No Reset is issued Reset of CAN protocol machine is issued if DCAN is in bus off state, DCAN will enter INIT state (CANC.0 = 1 && CANES.3 = 1) Cautions: 1. Issuing TLRES bit may violate the minimum recovery time as defined in ISO11898. 2. If no receive buffer is desired, define one receive buffer and disable this buffer with the REDEF function. CADD1 CADD0 0 0 1 1 0 1 0 1 Setting prohibited DCAN Address definition F600H to F7DFH (reset value) User's Manual U16504EE1V1UD00 289 Chapter 16 CAN Controller 16.14 Baudrate Generation (1) Bit Rate Prescaler Register This register sets the clock for the DCAN (internal DCAN clock) and the number of clocks per time quantum (TQ). BRPRS can be set with an 8-bit memory manipulation instruction. RESET input sets BRPRS to 3FH. Figure 16-43: Symbol BRPRS 7 PRM1 R/W 6 R/W 5 R/W 4 R/W Bit Rate Prescaler (1/2) 3 R/W 2 R/W 1 R/W 0 R/W Address FFB8H After Reset 3FH PRM0 BRPRS5 BRPRS4 BRPRS3 BRPRS2 BRPRS1 BRPRS0 The PRMn (n = 0, 1) bits define the clock source for the DCAN operation. The PRM selector defines the input clock to the DCAN Macro and influences therefore all DCAN activities. Writing to the BRPRS register is only allowed during initialization mode. Any write to this register when INIT bit is set in CANC register and the initialization mode is not confirmed by the INITSTATE bit of CANES register can cause unexpected behaviour to the CAN bus. PRM1 0 0 1 1 PRM0 0 1 0 1 Input Clock Selector for DCAN Clock fX is input for DCAN fX/2 is input for DCAN fX/4 is input for DCAN CCLK is input for DCAN The BRPRSn bits (n = 0 to 5) define the number of DCAN clocks applied for one TQ. For BRPRSn (n = 0 to 5) two modes are available depending on the TLMODE bit in the SYNC1 register. 290 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-43: Bit Rate Prescaler (2/2) Setting of BRPRSn (n = 5 to 0) for TLMODE = 0: BRPRS5 0 0 0 0 . . . 1 1 1 1 1 1 BRPRS4 0 0 0 0 . . . 1 1 1 1 1 1 BRPRS3 0 0 0 0 . . . 1 1 1 1 1 1 BRPRS2 0 0 0 0 . . . 0 0 1 1 1 1 BRPRS1 0 0 1 1 . . . 1 1 0 0 1 1 BRPRS0 0 1 0 1 . . . 0 1 0 1 0 1 Bit Rate PrescalerNote 2 4 6 8 . 2 x BRPRSn[5-0] + 2 . 118 120 122 124 126 128 Note: The bit rate prescaler value represents the DCAN clocks per TQ. Setting of BRPRSn (n = 7 to 0) for TLMODE = 1: BRPRS7 BRPRS6 BRPRS5 BRPRS4 BRPRS3 BRPRS2 BRPRS1 BRPRS0 0 0 0 0 0 0 0 0 0 0 0 0 . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 . . . 1 1 1 1 1 1 0 0 0 0 . . . 1 1 1 1 1 1 0 0 0 0 . . . 0 0 1 1 1 1 0 0 1 1 . . . 1 1 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 Bit Rate Prescaler 1Note 2 3 4 . BRPRSn[7-0] +1 . 123 124 125 126 127 128 Note: When using this setting the user needs to assure that phase segment 2 consists of at least 3 TQ. Phase segment 2 is given by the difference of DBT - SPT each measured in units of TQ. BRPRS7 and BRPRS6 are located in the MASKC register. User's Manual U16504EE1V1UD00 291 Chapter 16 (2) CAN Controller Synchronization Control Registers 0 and 1 These registers define the CAN bit timing. They define the length of one data bit on the CAN bus, the position of the sample point during the bit timing, and the synchronization jump width. The range of resynchronization can be adapted to different CAN bus speeds or network characteristics. Additionally, some modes related to the baud rate can be selected in SYNC1 register. SYNC0 and SYNC1 can be read or written with an 8-bit memory manipulation instruction. RESET input sets SYNC0 to 18H. RESET input sets SYNC1 to 0EH. Figure 16-44: Symbol SYNC0 Symbol 7 SPT2 7 6 SPT1 6 5 SPT0 5 Synchronization Control Registers 0 and 1 (1/2) 4 DBT4 4 3 DBT3 3 SJW1 2 DBT2 2 SJW0 1 DBT1 1 SPT4 0 DBT0 0 SPT3 Address After Reset R/W FFB9H 18H R/W Address After Reset R/W FFBAH 0EH R/W SYNC1 TLMODE SOFC SAMP RXONLY The length of a data bit time is programmable via DBT[4-0]. DBT4 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 DBT3 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 DBT2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 DBT1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 DBT0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Data Bit Time Setting prohibited 8 x TQ 9 x TQ 10 x TQ 11 x TQ 12 x TQ 13 x TQ 14 x TQ 15 x TQ 16 x TQ 17 x TQ 18 x TQ 19 x TQ 20 x TQ 21 x TQ 22 x TQ 23 x TQ 24 x TQ 25 x TQ Setting prohibited Other than under Other than above 292 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-44: Synchronization Control Registers 0 and 1 (2/2) The position of the sample point within the bit timing is defined by SPT0n through SPT4n. SPT4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SPT3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 SPT2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 SPT1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 SPT0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Sample Point Position Setting prohibited 2 x TQ 3 x TQ 4 x TQ 5 x TQ 6 x TQ 7 x TQ 8 x TQ 9 x TQ 10 x TQ 11 x TQ 12 x TQ 13 x TQ 14 x TQ 15 x TQ 16 x TQ 17 x TQ Setting prohibited Other than under Other than above TLMODE 0 1 Resolution of Bit Rate Prescaler 1 unit of BRPRS[5-0] in BRPRS register equals 2 DCAN clocks, BRPRS[7-6] in MASKC register are disabled (compatible to older macro versions) 1 unit of BRPRS[7-0] in BRPRS and MASKC register equals 2 DCAN clocks, BRPRS[7-6] in MASKC register are enabledNote Note: The user needs to assure that phase segment 2 (TSEG2) consists of at least 3 TQ when using this setting. Phase segment 2 is given by the difference of DBT - SPT each measured in units of TQ. SJW0 and SJW1 define the synchronization jump width as specified in ISO 11898. SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronisation Jump Width 1 x TQ 2 x TQ 3 x TQ 4 x TQ User's Manual U16504EE1V1UD00 293 Chapter 16 Limits on defining the bit timing CAN Controller The sample point position needs to be programmed between 3TQNote and 17TQ, which equals a register value of 2 SPTxn 16 (n = 0, 1; x = 4 to 0). The number of TQ per bit is restricted to the range from 8TQ to 25TQ, which equals a register value of 7 DBTxn 24 (n = 0, 1; x = 4 to 0). The length of phase segment 2 (TSEG2) in TQ is given by the difference of TQ per bit (DBTxn) and the sample point position (SPTxn). Converted to register values the following condition applies: 2 DBTxn - SPTxn 8 (n = 0, 1; x = 4 to 0). The number of TQ allocated for soft synchronization must not exceed the number of TQ for phase segment 2, but SJWyn may have as many TQ as phase segment 2: SJWyn DBTxn - SPTxn - 1 (n = 0, 1; x = 4 to 0; y = 0, 1). Note: Sample point positions of 3 TQ or 4 TQ are for test purposes only. For the minimum number of TQ per bit time, 8TQ, the minimum sample point position is 5 TQ. Example: System clock: CAN parameter: fx Baud rate Sample Point SJW At first, calculate the overall prescaler value: fX 8 MHz ------------------------ = ---------------------------- = 16 500 KBaud Baudrate 16 can be split as 1 x 16 or 2 x 8. Other factors can not be mapped to the registers. Only 8 and 16 are valid values for TQ per bit. Therefore the overall prescaler value realized by BRPRSn is 2 or 1 respectively. With TLMODE = 0 the following register settings apply: Register value BRPRSn = 00h SYNC0n = A7h Description Clock selector = fx CAN Bit in TQ = 8 7 < (fx/Baudrate/bit rate prescaler) < 25] SYNC1n = 0zzz0100b sample point 75% = 6 TQ SJW 25% = 2 TQ z depends on the setting of: - Number of sampling points - Receive only function - Use of time stamp or global time system SPTx = 00101b SJWy = 01b Bit fields PRMn = 00b BRPRSx = 000000b DBTx = 00111b 8 MHz 500 kBaud 75% 25% 1 TQ equals 2 clocks & BRPRS6, 7 are disabled TLMODE = 0 294 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller With TLMODE = 1 the following register settings apply: Register values BRPRSn = 00h MASKCn = 00xx xxxxb SYNC0n = 6Fh CAN Bit in TQ = 16 7 < (fx/Baudrate/bit rate prescaler) < 25] SYNC1n = 1zzz 1101b sample point 75% = 12 TQ: SJW 25% = 4 TQ 1 TQ equals 1 clock, BRPRS 6, 7 are enabled z depends on the setting of: - Number of sampling points - Receive only function - Use of time stamp or global time system The receive-only mode can be used for baudrate detection. Different baudrate configurations can be tested without disturbing other CAN nodes on the bus. SPTn = 01011b SJWn = 11b TLMODE = 1 Description Clock selector = fx Bit fields PRMn = 00b BRPRSn = 0000 0000b DBTn = 01111b RXONLY 0 1 Normal operation Receive Only Operation Only receive operation, CAN does not activate transmit line Differences to CAN protocol in the receive-only mode: * The mode never sends an acknowledge, error frames or transmit messages. * The error counters do not count. The VALID bit in CANES reports if the DCAN interface receives any valid message. SAMP defines the number of sample points per bit as specified in the ISO-11898. SAMP 0 1 Bit Sampling Sample receive data one time at receive point Sample receive data three times and take majority decision at sample point SOFC works in conjunction with the SOFE and SOFSEL bits in the CAN Control Register CANC. For detailed information please refer to the bit description of that SFR register and the time function mode. SOFC 0 1 Start of Frame Control SOFE bit is independent from CAN bus activities SOFE bit will be cleared when a message for receive message 4 is received and SOF mode is selected Caution: CPU can read SYNC0/SYNC1 register at any time. Writing to the SYNC0/SYNC1 registers is only allowed during initialization mode. Any write to this register when INIT is set and the initialization mode is not confirmed by the INITSTATE bit can have unexpected behavior to the CAN bus. User's Manual U16504EE1V1UD00 295 Chapter 16 CAN Controller 16.15 Function Control 16.15.1 Transmit Control (1) Transmit control register This register controls the transmission of the DCAN-module. The transmit control register (TCR) provides complete control over the two transmit buffers and their status. It is possible to request and abort transmission of both buffers independently. TCR can be set with a an 8-bit memory manipulation instruction. RESET input sets TCR to 00H. Figure 16-45: Symbol TCR 7 TXP R/W 6 0 R 5 TXC1 R 4 TXC0 R Transmit Control Register (1/2) 3 TXA1 R/W 2 TXA0 R/W 1 TXRQ1 R/W 0 TXRQ0 R/W Address FFB1H After Reset 00H Caution: Don't use bit operations on this register. Also logical operations (read-modify-write) via software may lead to unexpected transmissions. Initiating a transmit request for buffer 1 while TXRQ0 is already set, is simply achieved by writing 02H or 82H. The status of the bits for buffer 0 is not affected by this write operation. TXP 0 1 Transmission Priority Buffer 0 has priority over buffer 1 Buffer 1 has priority over buffer 0 The user defines which buffer has to be send first in the case of both request bits are set. If only one buffer is requested by the TXRQn bits (n = 0, 1) bits, TXP bit has no influence. TXCn (n = 0, 1) shows the status of the first transmission. It is updated when TXRQn (n = 0, 1) is cleared. TXAn 0 Transmission Abort Flag Write: normal operation Read: no abort pending Write: aborts current transmission request for this buffer n Read: abort is pending 1 TXCn 0 1 Transmission Complete Flag Transmit was aborted / no data sent Transmit was complete / abort had no effect The TXAn bits (n = 0, 1) allow to free a transmit buffer with a pending transmit request. Setting the TXAn bit (n = 0, 1) by the CPU requests the DCAN to empty its buffer by clearing the respective TXRQn bit (n = 0, 1). 296 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-45: Transmit Control Register (2/2) The TXAn bits (n = 0, 1) have a dual function: 1. The CPU can request an abort by writing a "1" into the bit. 2. The DCAN signals whether such an request is still pending. The bit is cleared at the same time when the TXRQn bit (n = 0, 1) is cleared. The abort process does not affect any rules of the CAN protocol. A frame already started will continue to its end. An abort operation can cause different results dependent on the time it is issued. d) When an abort request is recognized by the DCAN before the start of the arbitration for transmit, the TXCn bit (n = 0, 1) is reset showing that the buffer was not send to other nodes. e) When the abort request is recognized during the arbitration and the arbitration is lost afterwards, the TXCn bit (n = 0, 1) is reset showing that the buffer was not send to other nodes. f) When the abort request is recognized during frame transmission and the transmission ends with an error afterwards, the TXCn bit (n = 0, 1) is reset showing that the buffer was not send to other nodes. g) When the abort request is recognized during the frame transmission and transmission ends without error. The TXCn bit (n = 0, 1) is set showing a successful transfer of the data. I.e the abort request was not issued. In all cases the TXRQn bit and the TXAn bit (n = 0, 1) bit will be cleared at the end of the abort operation, when the transmit buffer is available again. Cautions: 1. The bits are cleared when the INIT bit in CANC register is set. 2. Writing a 0 to TXAn (n = 0, 1) bit has no influence 3. Do not perform read-modify-write operations on TCR. The TXCn bit (n = 0, 1) are updated at the end of every frame transmission or abort. TXRQn 0 Transmission Request Flag Write: no influence Read: transmit buffer is free Write: request transmission for buffer n Read: transmit buffer is occupied by former transmit request 1 The transmit request bits are checked by the DCAN immediately before the frame is started. The order in which the TXRQn bit (n = 0, 1) will be set does not matter as long as the first requested frame is not started on the bus. The TXRQn bit (n = 0, 1) have dual function: * 1. Request the transmission of a transmit buffer. * 2. Inform the CPU whether a buffer is available or if it is still occupied by a former transmit request. Setting the transmission request bit requests the DCAN to sent the buffer contents onto the bus. The DCAN clears the bit after completion of the transmission. Completion is either a normal transfer without error or an abort request. User's Manual U16504EE1V1UD00 297 Chapter 16 CAN Controller An error during the transmission does not influence the transmit request status. The DCAN will automatically retry the transfer. Cautions: 1. The bits are cleared when the INIT bit in CANC is set. A transmission already started will be finished but not retransmitted in case of an error. 2. Writing a 0 to TXRQ0 bit has no influence. 3. Do not use bit operations on this register. 4. Do not change data in transmit buffer when the corresponding TXRQ bit is set. 16.15.2 Receive Control The receive message register mirrors the current status of the first 8 receive buffers. Each buffer has one status bit in this register. This bit is always set when a new message is completely stored out of the shadow buffer into the associated buffer. The CPU can easily find the last received message during receive interrupt handling. The bits in this register always correspond to the DN bit in the data buffers. They are cleared when the CPU clears the DN bit in the data buffer. The register itself is read only. (1) Receive message register This register shows receptions of messages of the DCAN-module. More than one bit set is possible. RMES can be read with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets RMES to 00H. Figure 16-46: Symbol RMES 7 DN7 R 6 DN6 R 5 DN5 R 4 DN4 R Receive Message Register 3 DN3 R 2 DN2 R 1 DN1 R 0 DN0 R Address FFB2H After Reset 00H This register is read only and it is cleared when the INIT bit in CANC register is set. DN 0 1 Data New Bit for Message n (n = 0...7) No message received on message n or CPU has cleared DN bit in message n Data received in message n that was not acknowledged by the CPU DN0 bit has no meaning when receive buffer 0 is configured for mask operation in the mask control register. DN2 bit has no meaning when receive buffer 2 is configured for mask operation in the mask control register. 298 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.15.3 Mask Control The mask control register defines whether the DCAN compares all identifier bits or if some bits are not used for comparison. This functionality is provided by the use of the mask information. The mask information defines for each bit of the identifier whether it is used for comparison or not. The DCAN uses a receive buffer for this information, when it is enabled by the mask control register. In this case this buffer is not used for normal message storage. Unused bytes can be used for application needs. (1) Mask control register This register controls the mask function applied to any received message. MASKC can be written with an 8-bit memory manipulation instruction. RESET input sets MASKC to 00H. Figure 16-47: Symbol 7Note R/W 6Note R/W 5 SSHT R/W 4 AL R/W Mask Control Register (1/2) 3 0 R 2 GLOBAL R/W 1 MSK1 R/W 0 MSK0 R/W Address FFBBH After Reset 00H MASKC BRPRS7 BRPRS6 Note: BRPRS[7 - 6] are only enable if TLMODE is set to 1. Caution: This register is readable at any time. Writing to the MASKC register is only allowed during initialization mode. Any write to this register when INIT bit is set and the initialization mode is not confirmed by the INITSTATE bit can have unexpected behavior to the CAN bus. MSK0 0 1 MSK1 0 1 GLOBAL 0 1 Normal operation Mask 0 Enable Receive buffer 0 and 1 in normal operation Receive buffer 0 is mask for buffer 1 Mask 1 Enable Receive buffer 2 and 3 in normal operation Receive buffer 2 is mask for buffer 3 Enable Global Mask Highest defined mask is active for all following buffers User's Manual U16504EE1V1UD00 299 Chapter 16 Figure 16-47: CAN Controller Mask Control Register (2/2) SSHT 0 1 AL x 0 Single shot mode disabled Function Single shot mode enabled; no re-transmission when an error occurs. Transmit message will not be queued for a second transmit request when the arbitration was lost Single shot mode enabled; no re-transmission when an error occurs. Transmit message will be queued for a second transmit request when the arbitration was lost. 1 1 BRPRS7 0 0 1 1 BRPRS6 0 1 0 1 Prescaler values Selects 0 - 64 DCAN clocks per time quanta Selects 65 - 128 DCAN clocks per time quanta Selects 129 - 192 DCAN clocks per time quanta Selects 193 - 256 DCAN clocks per time quanta The following table shows which compare takes place for the different receive buffers. The ID in this table always represents the ID stored in the mentioned receive buffer. The table also shows which buffers are used to provide the mask information and therefore do not receive messages. A global mask can be used for standard and extended frames at the same time. The frame type is only controlled by the IDE bit of the receiving buffer. Table 16-26: GLOBAL MSK1 MSK0 X 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 Mask Operation Buffers Receive Buffer Operation Normal One mask One mask Two masks Global mask Two normal, rest global mask One mask, rest global mask 0 Compare ID Mask0 Compare ID Mask0 Mask0 Compare ID Mask0 1 Compare ID Compare ID & mask0 Compare ID Compare ID & mask0 2 Compare ID Compare ID Mask1 Mask1 3 Compare ID Compare ID Compare ID & mask1 Compare ID & mask1 Compare ID Compare ID Compare ID 4-15 Compare ID Compare ID Compare ID Compare ID & mask0 & mask1 & mask1 Compare Compare ID & mask0 ID & mask0 Compare ID Compare ID & mask0 Mask1 Mask1 300 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Priority of receive buffers during compare It is possible that more than one receive buffer is configured to receive a particular message. For this case an arbitrary rule for the storage of the message into one of several matching receive buffers becomes effective. The priority of a receive buffers depends on its type defined by the setup of the mask register in first place and its number in second place. The rules for priority are: * All non-masked receive buffers have a higher priority than the masked receive buffer. * Lower numbered receive buffers have higher priority. Examples: 1. 2. 3. All RX buffers are enabled to receive the same standard identifier 0x7FFH. Result: the message with identifier 0x7FFH is stored in RX0. In difference to the previous set up, the mask option is set for RX2. Again the message 0x7FFH is stored in buffer in RX0. If additionally RX0 is configured as a mask, the message will be stored in RX4. User's Manual U16504EE1V1UD00 301 Chapter 16 16.15.4 Special Functions (1) Redefinition control register CAN Controller This register controls the redefinition of an identifier of a received buffer. REDEF can be written with an 1-bit or an 8-bit memory manipulation instruction. RESET input sets REDEF to 00H. Figure 16-48: Symbol REDEF <7> DEF R/W 6 0 R 5 0 R 4 0 R Redefinition Control Register (1/2) 3 SEL3 R/W 2 SEL2 R/W 1 SEL1 R/W 0 SEL0 R/W Address FFB3H After Reset 00H The redefinition register provides a way to change identifiers and other control information for one receive buffer, without disturbing the operation of the other buffers. DEF 0 1 Normal operation Redefine Permission Bit Receive operation for selected message is disabled. CPU can change definition data for this message. This bit is cleared when INIT bit in CANC is set. 302 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller Figure 16-48: Redefinition Control Register (2/2) SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Buffer selection (n =0...15) Buffer 0 is selected for redefinition Buffer 1 is selected for redefinition Buffer 2 is selected for redefinition Buffer 3 is selected for redefinition Buffer 4 is selected for redefinition Buffer 5 is selected for redefinition Buffer 6 is selected for redefinition Buffer 7 is selected for redefinition Buffer 8 is selected for redefinition Buffer 9 is selected for redefinition Buffer 10 is selected for redefinition Buffer 11 is selected for redefinition Buffer 12 is selected for redefinition Buffer 13 is selected for redefinition Buffer 14 is selected for redefinition Buffer 15 is selected for redefinition Setting prohibited Other than above Cautions: 1. Keep special programming sequence. Failing to do so can cause inconsistent data or loss of receive data. 2. Do not change DEF bit and SEL bit at the same time. Change SEL bit only when DEF bit is cleared. 3. Write first SEL with DEF cleared. Write than SEL with DEF, or use bit manipulation instruction. Only clear DEF bit by keeping SEL or use bit manipulation instruction. Setting the redefinition bit removes the selected receive buffer from the list of possible ID hits during identifier comparisons. Setting the DEF bit will not have immediate effect, if DCAN is preparing to store or is already in progress of storing a received message into the particular buffer. In this case the redefinition request is ignored for the currently processed message. The application should monitor the DN flag before requesting the redefinition state for a particular buffer. A DN flag set indicates a new message that arrived or a new message that is in progress of being stored to that buffer. The application should be prepared to receive a message immediately after redefinition state was set. The user can identify this situation because the data new bit (DN) in the receive buffer will be set. This is of special importance if it is used together with a mask function because in this case the DCAN also writes the identifier part of the message to the receive buffer. Then the application needs to re-write the configuration of the message buffer. User's Manual U16504EE1V1UD00 303 Chapter 16 CAN Controller 16.16 Interrupt Information 16.16.1 Interrupt Vectors The DCAN peripheral supports four interrupt sources as shown in the following table. Table 16-27: Function Error Receive Transmit buffer 0 Transmit buffer 1 Interrupt Sources Source Interrupt Flag CEIF CRIF CTIF0 CTIF1 Error counter Overrun error Wake up Received frame is valid TXRQ0 is cleared TXRQ1 is cleared 16.16.2 Transmit Interrupt The transmit interrupt is generated when all following conditions are fulfilled: * The transmit interrupt 0 is generated when TXRQ0 bit is cleared. * The transmit interrupt 1 is generated when TXRQ1 bit is cleared. Clearing of these bits releases the buffer for writing a new message into it. This event can occur due to a successful transmission or due to an abort of a transmission. Only the DCAN can clear this bit. The CPU can only request to clear the TXRQn bit by setting the ABORTn bit (n = 0, 1). 16.16.3 Receive Interrupt The receive interrupt is generated when all of the following conditions are fulfilled: * CAN protocol part marks received frame valid. * The received frame passes the acceptance filter. In other words, a message buffer with an identifier/mask combination fits to the received frame. * The memory access engine successfully stored data in the message buffer. * The message buffer is marked for interrupt generation with ENI bit set. The memory access engine can delay the interrupt up to the 7th bit of the next frame because of its compare and store operations. 304 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.16.4 Error Interrupt The error interrupt is generated when any of the following conditions are fulfilled: * Transmission error counter (BOFF) changes its state. * Transmission error counter status (TECS) changes its state. * Reception error counter status (RECS) changes its state. * Overrun during RAM access (OVER) becomes active. * The wake-up condition (WAKE) becomes active. The wake-up condition activates an internal signal to the interrupt controller. In order to receive further error interrupts generated by other conditions, the CPU needs to clear the WAKE bit in CANES register every time a wake-up condition was recognized. No further interrupt can be detected by the CPU as long as the WAKE bit is set. User's Manual U16504EE1V1UD00 305 Chapter 16 CAN Controller 16.17 Influence of the standby Function of the CAN Controller 16.17.1 CPU Halt Mode The CPU halt mode is possible in conjunction with DCAN Sleep mode. 16.17.2 CPU Stop Mode The DCAN stops any activity when its clock supply stops due to a CPU Stop mode issued. This may cause an erroneous behaviour on the CAN bus. Entering the CPU Stop Mode is not allowed when the DCAN is in normal mode, i.e. online to the CAN bus. The DCAN will reach an overrun condition, when it receives clock supply again. CPU Stop mode is possible when the DCAN was set to initialization state, sleep mode or stop mode beforehand. Note that the CPU will not be started again if the DCAN Stop mode was entered previously. 16.17.3 DCAN Sleep Mode The DCAN Sleep mode is intended to lower the power consumption during phases where no communication is required. The CPU requests the DCAN Sleep mode. The DCAN will signal with the WAKE bit, if the request was granted or if it is not possible to enter the sleep mode due to ongoing bus activities. After a successful switch to the DCAN Sleep mode, the CPU can safely go into halt, watch or stop mode. However, the application needs to be prepared that the DCAN cancels the sleep mode any time due to bus activities. If the wake-up interrupt is serviced, the CPU Stop mode has not to be issued. Otherwise the CPU will not be released from CPU Stop mode even when there is ongoing bus activity. The wake-up is independent from the clock. The release time for the CPU Stop mode of the device is of no concern because the DCAN synchronizes again to the CAN bus after clock supply has started. 306 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller The following example sketches the general approach on how to enter the DCAN Sleep mode. Note that the function may not return for infinite time when the CAN bus is busy. The user may apply time out controls to avoid excessive run-times. Code example: DCAN_Sleep_Mode(void){ CANES = 0x02; CANC = 0x04 while (CANES & 0x02) { CANES = 0x02; CANC = 0x04; } } // clear Wake bit // request DCAN Sleep mode // check if DCAN Sleep mode was accepted // try again to get DCAN asleep The following code example assures a safe transition into CPU Stop mode for all timing scenarios of a suddenly occurring bus activity. The code prevents that the CPU gets stuck with its oscillator stopped despite CAN bus activity. Code example: ........ DCAN_Sleep_Mode; ........ //any application code //request and enter DCAN sleep mode //any application code DI(); //disable interrupts Note NOP; NOP; if (wakeup_interrupt_occurred == FALSE) // the variable wakeup_interrupt occurred // needs to be initialized at system reset // and it needs to be set TRUE when servicing // the wake-up interrupt. { CPU_STOP; //enter CPU Stop mode } NOP:Note NOP: NOP; EI(); // enable interrupts ......... // resume with application code Note: The interrupt acknowledge needs some clock cycles (depends on host core). In order to prevent that the variable wakeup_interrupt_occurred is already read before DI(); becomes effective some NOP-instruction have to be inserted. As well the number of NOP-instructions after the CPU Stop instruction is dependent on the host core. The given example is tailored for 78K0. User's Manual U16504EE1V1UD00 307 Chapter 16 16.17.4 DCAN Stop Mode CAN Controller The CPU requests this mode from DCAN. The procedure equals the request for DCAN Sleep mode. The DCAN will signal with the WAKE bit, if the request was granted or if it is not possible to enter the DCAN Stop mode due to ongoing bus activities. After a successful switch to the DCAN Stop mode, the CPU can safely go into halt, watch or stop mode without any precautions. The DCAN can only be woken up by the CPU. Therefore the CPU needs to clear the SLEEP bit in the CANC register. This mode reduces the power consumption of the DCAN to a minimum. Code example: DCAN_Stop_Mode(void){ CANES = 0x02; CANC = 0x06 while (CANES & 0x02) { CANES = 0x02; CANC = 0x06; } } // clear Wake bit // request DCAN Stop mode // check if DCAN Stop mode was accepted // try again to get DCAN into stop mode 308 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.18 Functional Description by Flowcharts 16.18.1 Initialization Figure 16-49: Initialization Flow Chart RESET Software Init set INIT=1 in CANC set BRPRS SYNC0/1 Initilialize message and mask data set MCNT MASKC Write for BRPRS SYNC0/1 MCNT MASKC is now disabled Clear INIT=0 in CANC End Initialization User's Manual U16504EE1V1UD00 309 Chapter 16 16.18.2 Transmit Preparation Figure 16-50: CAN Controller Transmit Preparation Transmit =1 TXRQn Wait or Abort or Try other Buffer =0 Write data Select Priority TXP Set TXRQn = 1 End Transmit 310 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.18.3 Abort Transmit Figure 16-51: Transmit Abort Transmission Abort Set TXAn =1 TXRQn =0 =0 TXCn =1 Transmit was aborted Transmit was successful before ABORT End Transmission Abort User's Manual U16504EE1V1UD00 311 Chapter 16 16.18.4 Handling by the DCAN Figure 16-52: CAN Controller Handling of Semaphore Bits by DCAN-Module Data Storage Warns that data will be changed Write DN = 1 MUC = 1 Write Identifier bytes Only for buffers that are declared for mask operation Write Data bytes Write DN = 1 MUC = 0 DLC Data is changed. MUC = 0 signals stable data End Data Storage 312 User's Manual U16504EE1V1UD00 Chapter 16 CAN Controller 16.18.5 Receive Event Oriented Figure 16-53: Receive with Interrupt, Software Flow Receive Interrupt scans RMES or DN bits to find message Clear DN bit Uses CLR1 Command No read or process data DN = 0 AND MUC = 0 Yes Data was changed by CAN during the processing Clear Interrupt End Receive interrupt User's Manual U16504EE1V1UD00 313 Chapter 16 16.18.6 Receive Task Oriented Figure 16-54: CAN Controller Receive, Software Polling Receive Polled Clear DN bit Uses CLR1 command Read or process data No DN = 0 AND MUC = 0 Yes Data was changed by CAN during the processing End Receive Polled 314 User's Manual U16504EE1V1UD00 Chapter 17 17.1 LCD Controller/Driver Functions LCD Controller / Driver The functions of the LCD controller/driver incorporated in the PD780828A Subseries are listed below. (1) (2) Automatic output of segment signals and common signals is possible by automatic reading of the display data memory. Display mode * 1/4 duty (1/3 bias) (3) (4) Any of four frame frequencies can be selected in each display mode. Maximum of 28 segment signal outputs (S0 to S27); 4 common signal outputs (COM0 to COM3). All segment outputs can be switched to input/output ports. P47/S0 to P40/S7 is byte-wise switchable. P87/S8 to P80/S15, P97/S16 to P90/S23 and P37/S24 to P34/S27 are bitwise switchable. The maximum number of displayable pixels is shown in Table 17-1. Table 17-1: Bias Method 1/3 Time Division 4 Maximum Number of Display Pixels Common Signals Used COM0 to COM3 Maximum Number of Display Pixels 112 (28 segments x 4 commons) 17.2 LCD Controller/Driver Configuration The LCD controller/driver consists of the following hardware. Table 17-2: Item LCD Controller/Driver Configuration Configuration Segment signals: 28 Display outputs Segment signal with alternate function: 28 Common signals: 4 (COM0 to COM3) Control registers LCD display mode register (LCDM) LCD display control register (LCDC) User's Manual U16504EE1V1UD00 315 Chapter 17 LCD Controller / Driver Figure 17-1: LCD Controller/Driver Block Diagram Internal bus Display data memory FA7FH 76543210 FA68H 76543210 FA67H 76543210 LCD display mode register (LCDM) F A64H 76543210 LCDON LCDM6 LCDM5 LCDM4 LCD display control register (LCDC) LIPS Port function register (PFn) (n = 3, 4, 8, 9) 3 LCD clock selector fLCD 3210 selector ... ... ... 3210 selector 3210 ... ... ... selector 3210 selector Timing controller ... ... ... ... ... ... Segment selector Note ... ... ... ... ... Note Note ... ... ... Note Common driver LCD driver voltage controller P47 output buffer P90 output buffer P77 output buffer P50 output buffer S0/P47 ... ... ... ... S23/P90 S24/P37 ... ... ... S27/P34 COM0 COM1 COM2 COM3 V LCD Remark: Segment driver Figure 17-2: LCD Clock Select Circuit Block Diagram fx/2 14 Prescaler fLCD /2 fLCD/2 f LCD /2 f LCD 3 2 Selector LCDCL 3 LCDM6 LCDM5 LCDM4 LCD display mode register Internal bus Remarks: 1. LCDCL: LCD clock 2. fLCD: LCD clock frequency 316 User's Manual U16504EE1V1UD00 Chapter 17 LCD Controller / Driver 17.3 LCD Controller/Driver Control Registers The LCD controller/driver is controlled by the following two registers. * LCD display mode register (LCDM) * LCD display control register (LCDC) (1) LCD display mode register (LCDM) This register enables/disables the LCD and selects the LCD clock. LCDM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears LCDM to 00H. Figure 17-3: LCD Display Mode Register (LCDM) Format Symbol 7 6 5 4 3 0 2 0 1 0 0 0 Address After Reset R/W FF90H 00H R/W LCDM LCDON LCDM6 LCDM5 LCDM4 LCDON 0 1 LCD Enable/Disable Display off (all segment outputs are non-select signal outputs) Display on LCDM6 0 0 0 0 LCDM5 0 0 1 1 LCDM4 0 1 0 1 LCD Clock Selection (fX = 8.00 MHz) fX/217 (61 Hz) fX/216 (122 Hz) fX/215 (244 Hz) fX/214 (488 Hz) Setting prohibited Other than above Remark: fX = Main system clock oscillation frequency (at 8.00 MHz) User's Manual U16504EE1V1UD00 317 Chapter 17 LCD Controller / Driver (2) LCD display control register (LCDC) This register sets cutoff of the current flowing to split resistors for LCD drive voltage generation and switchover between segment output and input/output port functions. LCDC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears LCDC to 00H. Figure 17-4: LCD Display Control Register (LCDC) Format Symbol LCDC 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 LIPS Address After Reset R/W FF92H 00H R/W LIPS 0 1 LCD Driving Power Supply Selection Does not supply power to LCD Supplies power to LCD from VDD pin Caution: Set bit 7 to 1 and bit 1 to bit 6 to 0. 17.4 LCD Controller/Driver Settings LCD controller/driver settings should be performed as shown below. <1> <2> <3> <4> Set the initial value in the display data memory (FA64H to FA7FH). Set the pins to be used as segment outputs in port function registers (PF3, PF4, PF8 and PF9). Set the LCD power supply in the LCD display control register (LCDC). Set the LCD clock in the LCD display mode register (LCDM). Next, set data in the display data memory according to the display contents. 318 User's Manual U16504EE1V1UD00 Chapter 17 LCD Controller / Driver 17.5 LCD Display Data Memory The LCD display data memory is mapped onto addresses FA64H to FA7FH. The data stored in the LCD display data memory can be displayed on an LCD panel by the LCD controller/driver. Figure 17-5 shows the relationship between the LCD display data memory contents and the segment outputs/common outputs. Any area not used for display can be used as normal RAMNote. Figure 17-5: Relationship between LCD Display Data Memory Contents and Segment/Common Outputs b7 b6 b5 b4 b3 b2 b1 b0 S0/P47 S1/P46 S2/P45 S3/P44 Address FA7FH FA7CH FA7DH FA7CH FA66H FA65H FA64H S25/P36 S26/P35 S27/P34 COM3 COM2 COM1 COM0 Caution: The higher 4 bits of the LCD display data memory do not incorporate memory. Be sure to set them to 0. The data of S0 is stored at the highest address in the LCD display data memory. Remark: Note: RESET clears the LCD Display Data Memory to 00H. User's Manual U16504EE1V1UD00 319 Chapter 17 LCD Controller / Driver 17.6 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the LCD drive voltage VLCD). The light goes off when the potential difference becomes VLCD or lower. As an LCD panel deteriorates if a DC voltage is applied in the common signals and segment signals, it is driven by AC voltage. (1) Common signals For common signals, the selection timing order is as shown in Table 17-3, and operations are repeated with these as the cycle. Table 17-3: COM Signals COM Signal COM0 Time Division 4-Time Division COM1 COM2 COM3 (2) Segment signals Segment signals correspond to a 28-byte LCD display data memory (FA64H to FA7FH). Each display data memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the COM0, COM1, COM2 and COM3 timings respectively, and if the value of the bit is 1, it is converted to the selection voltage. If the value of the bit is 0, it is converted to the non-selection voltage and send to a segment pin (S0 to S27) (S27 to S0 have an alternate function as input/output port pins). Consequently, it is necessary to check what combination of front surface electrodes (corresponding to the segment signals) and rear surface electrodes (corresponding to the common signals) of the LCD panel to be used to form the display pattern. Then write a bit data corresponding on a one-to-one basis with the pattern to be displayed. Bits 4 to 7 are fixed at 0. 320 User's Manual U16504EE1V1UD00 Chapter 17 (3) LCD Controller / Driver Common signal and segment signal output waveforms The voltages shown in Table 17-4 are output in the common signals and segment signals. The VLCD ON voltage is only produced when the common signal and segment signal are both at the selection voltage; other combinations produce the OFF voltage. Table 17-4: Segment Common Select Level Non-Select Level VLC0, VSS1 VLC2, VLC1 LCD Drive Voltage Select Level VSS1, VLC0 -VLCD, +VLCD Non-Select Level VLC1, VLC2 -1/3 VLCD, +1/3 VLCD -1/3 VLCD, +1/3 VLCD -1/3 VLCD, +1/3 VLCD Figure 17-6 shows the common signal waveform, and Figure 17-7 shows the common signal and segment signal voltages and phases. Figure 17-6: Common Signal Waveform VLC0 COMn (Divided by 4) TF = 4 x T VLC1 VLC2 VSS VLCD Remark: T : One LCDCL cycle TF : Frame frequency Figure 17-7: Common Signal and Segment Signal Voltages and Phases Selected Not selected VLC0 Common signal VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS T T VLCD Segment signal VLCD Remark: T : One LCDCL cycle User's Manual U16504EE1V1UD00 321 Chapter 17 LCD Controller / Driver 17.7 Supplying LCD Drive Voltage VLC0, VLC1, and VLC2 The PD780828A Subseries have a split resistor to create an LCD drive voltage, and the drive voltage is fixed to 1/3 bias. To supply various LCD drive voltages, internal VDD or external VLCD supply voltage can be selected. Table 17-5: LCD Drive Voltage Supply Bias Method 1/3 Bias Method VLC0 2/3 VLC0 1/3 VLC0 LCD Drive Voltage VLC0 VLC1 VLC2 Figure 17-8 shows an example of supplying an LCD drive voltage from an internal source according to Table 17-5. Figure 17-8: Example of Connection of LCD Drive Power Supply (1/2) (a) To supply LCD drive voltage from VDD VDD LIPS (= 1) P-ch Leave V LCD pin open V LC0 R V LC1 VLCD V LC2 R V SS V SS V LCD = VDD R 322 User's Manual U16504EE1V1UD00 Chapter 17 Figure 17-8: LCD Controller / Driver Example of Connection of LCD Drive Power Supply (2/2) (b) To supply LCD drive voltage from external source VDD VDD r1 LIPS (= 0) P-ch V LCD r2 VLC0 R VLC1 VLCD VLC2 R VSS VSS 3R r 2 3R r2 + 3R r1 + r 1 r 2 R VSS VLCD = x VDD User's Manual U16504EE1V1UD00 323 Chapter 17 LCD Controller / Driver 17.8 Display Mode 17.8.1 4-time-division display example Figure 17-10, "4-Time-Division LCD Panel Connection Example," on page 325 shows the relationship between a 4-time-division type 10-digit LCD panel and the display pattern shown in Figure 17-9, "4Time-Division LCD Display Pattern and Electrode Connections," on page 324 and the PD780828A Subseries segment signals (S0 to S19) in conjunction with common signals (COM0 to COM3). The display example is "1234567890". The display data memory contents (addresses FA7FH to FA6CH) correspond to this. An explanation is given here taking the example of the 5th digit "6" (). In accordance with the display pattern in Figure 17-9, "4-Time-Division LCD Display Pattern and Electrode Connections," on page 324, selection and non-selection voltages must be send to pins S8 and S9 as shown in Table 17-6 at the COM0 to COM3 common signal timings. Table 17-6: Selection and Non-Selection Voltages (COM0 to COM3) Segment Common COM0 COM1 COM2 COM3 S8 S NS S NS S9 S S S S Remark: S: Selection, NS: Non-selection From this, it can be seen that 0101 (COM0 is LSB) must be prepared in the display data memory (address FA77H) corresponding to S8. Examples of the LCD drive waveforms between S8 and the COM0 and COM1 signals are shown in Figure 17-11, "4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)," on page 326 (for the sake of simplicity, waveforms for COM2 and COM3 have been omitted). When S8 carries the selection voltage at the COM0 selection timing, it can be seen that the +VLCD/-VLCD AC square wave, which is the LCD illumination (ON) level, is generated. Figure 17-9: 4-Time-Division LCD Display Pattern and Electrode Connections S2n COM0 COM1 COM2 COM3 S2n + 1 Remark: n = 0 to 9 324 User's Manual U16504EE1V1UD00 Chapter 17 Figure 17-10: LCD Controller / Driver 4-Time-Division LCD Panel Connection Example Timing strobes COM3 COM2 COM1 COM0 BIT0 BIT1 BIT2 BIT3 1 FA7FH E D C B A 9 8 7 6 5 4 3 2 1 0 FA6FH E D FA6CH 1 1 0 S0 S1 S2 S3 S4 S5 S6 S7 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 1 0 1 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 Data memory address 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 1 010 111 100 0 1 1 0 0 0 0 0 101 0 0 0 1 LCD panel 1 0 1 11 01 11 01 0 S8 User's Manual U16504EE1V1UD00 325 Chapter 17 LCD Controller / Driver Figure 17-11: 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) TF VLC0 COM0 VLC1 VLC2 VSS VLC0 COM1 VLC1 VLC2 VSS VLC0 COM2 VLC1 VLC2 VSS VLC0 COM3 VLC1 VLC2 VSS VLC0 S8 VLC1 VLC2 VSS +VLCD +1/3VLCD COM0 to S8 0 -1/3VLCD -VLCD +VLCD +1/3VLCD COM1 to S8 0 -1/3VLCD -VLCD 326 User's Manual U16504EE1V1UD00 Chapter 17 LCD Controller / Driver 17.9 Cautions on Emulation To perform debugging with an in-circuit emulator, the LCD timer control register (LCDTM) must be set. LCDTM is a register used to figure the I/O board (IE-78K0-NS-P04) appropriately. 17.9.1 LCD timer control register (LCDTM) LCDTM is a write-only register that controls supply of the LCD-clock. Unless LCDTM is set, the LCD controller/ driver does not operate. Therefore, set bit 1 (TMC21) of LCDTM to 1 when using the LCD controller/driver. Figure 17-12: LCD Timer Control Register (LCDTM) Format Symbol LCDTM 7 1 6 0 5 0 4 0 3 0 2 0 1 TMC21 0 0 Address After Reset R/W FF93H 00H W TMC21 0 1 LCD Clock Supply Control LCD controller/driver stop mode (supply of LCD clock is stopped) LCD controller/driver operating mode (supply of LCD clock is enabled) Cautions: 1. LCDTM is a special register that must be set when debugging is performed with an in-circuit emulator. Even if this register is used, the operation of the PD780828A Subseries is not affected. However, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. Bits 7 to 2, and bit 0 must be set to 0. User's Manual U16504EE1V1UD00 327 [MEMO] 328 User's Manual U16504EE1V1UD00 Chapter 18 18.1 Sound Generator Function Sound Generator The sound generator has the function to operate an external speaker. The following two signals are supplied by the sound generator. (1) Basic cycle output signal (with/without amplitude) A buzzer signal with a variable frequency in a range of 0.5 to 3.8 KHz (at fX = 8.38 MHz) can be created. The amplitude of the basic cycle output signal can be varied by ANDing the basic cycle output signal with the 7-bit-resolution PWM signal, to achieve control of the volume. (2) Amplitude output signal A PWM signal with a 7-bit resolution for variable amplitude can be generated independently. Figure 19-1 shows the sound generator block diagram and Figure 19-2 shows the concept of each signal. Figure 18-1: Sound Generator Block Diagram Inter nal bus Sound generator control register (SGCR) TCE SGOB SGCL2 SGCL1 SGCL0 SGCL0 fX 2 Prescaler Selector fSG1 Selector 1/2 fSG2 5-bit counter Clear Selector Comparator 1/2 SGO/ SGOF/ P60 PWM amplitude Comparator S Q R SGOB PCL/ SGOA/ P61 7 4 SGBR3 SGBR2 SGBR1 SGBR0 SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0 P61 output latch Clock output control circuit (PCL) PM61 Sound generator buzzer control register (SGBR) Sound generator amplitude register (SGAM) Port mode register 6 (PM6) Internal bus User's Manual U16504EE1V1UD00 329 Chapter 18 Figure 18-2: Sound Generator Concept of Each Signal Basic cycle output SGOF (without amplitude) Amplitude output SGOA Basic cycle output SGO (with amplitude) 18.2 Sound Generator Configuration The sound generator consists of the following hardware. Table 18-1: Item Counter SG output Sound Generator Configuration Configuration 8 bits x 1, 5 bits x 1 SGO/SGOF (with/without append bit of basic cycle output) SGOA (amplitude output) Sound generator control register (SGCR) Sound generator buzzer control register (SGBR) Sound generator amplitude register (SGAM) Control register 18.3 Sound Generator Control Registers The following three types of registers are used to control the sound generator. * Sound generator control register (SGCR) * Sound generator buzzer control register (SGBR) * Sound generator amplitude control register (SGAM) 330 User's Manual U16504EE1V1UD00 Chapter 18 (1) Sound Generator Sound generator control register (SGCR) SGCR is a register which sets up the following four types. * Controls sound generator output * Selects output of sound generator * Selects sound generator input frequency fSG1 * Selects 5-bit counter input frequency fSG2 SGCR is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SGCR to 00H. Figure 18-3 shows the SGCR format. Figure 18-3: Sound Generator Control Register (SGCR) Format (1/2) Symbol SGCR 7 TCE 6 0 5 0 4 0 3 SGOB 2 1 0 Address After Reset R/W FFC0H 00H R/W SGCL2 SGCL1 SGCL0 TCE 0 1 Sound Generator Output Selection Timer operation stopped SGOF/SGO and SGOA for low-level output Sound generator operation SGOF/SGO and SGOA for output Caution: Remark: Before setting the TCE bit, set all the other bits. SGOF : SGO : SGOA : Basic cycle signal (without amplitude) Basic cycle signal (with amplitude) Amplitude signal SGOB 0 1 Sound Generator Output Selection Selects SGOF and SGOA outputs Selects SGO and PCL outputs SGCL2 0 0 1 1 SGCL1 0 1 0 1 5-Bit Counter Input Frequency fSG2 Selection fSG2 = fSG1/25 fSG2 = fSG1/26 fSG2 = fSG1/27 fSG2 = fSG1/28 User's Manual U16504EE1V1UD00 331 Chapter 18 Figure 18-3: Sound Generator Sound Generator Control Register (SGCR) Format (2/2) SGCL0 0 1 Sound Generator Input Frequency Selection fSG1 = fX/2 fSG1 = fX Cautions: 1. When rewriting SGCR to other data, stop the timer operation (TCE = 0) beforehand. 2. Bits 4 to 6 must be set to 0. Table 18-2: Maximum and Minimum Values of the Buzzer Output Frequency Maximum and Minimum Values of Buzzer Output SGCL2 SGCL1 SGCL0 fSG2 fSG1/26 fSG1/25 fSG1/27 fSG1/26 fSG1/28 fSG1/27 fSG1/29 fSG1/28 fX = 8 MHz Max. (KHz) 3.677 7.354 1.838 3.677 0.919 1.838 0.460 0.919 Min. (KHz) 1.953 3.906 0.976 1.953 0.488 0.976 0.244 0.488 fX = 8.38 MHz Max. (KHz) 3.851 7.702 1.926 0.481 0.963 1.926 0.481 0.963 Min. (KHz) 2.046 4.092 1.024 2.046 0.512 1.024 0.256 0.512 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 The sound generator output frequency fSG can be calculated by the following expression. fSG = 2 (SGCL0 - SGCL1 - 2 x SGCL2 - 7) x {fX / (SGBR + 17)} Substitute 0 or 1 for SGCL0 to SGCL2 in the above expression. Substitute a decimal value to SGBR. For fX = 8 MHz, SGCL0 to SGCL2 is (1, 0, 0), and SGBR0 to SGBR3 is (1, 1, 1, 1), SGBR = 15, then fSG is retrieved as fSG = 2 (1 - 0 - 2 x 0 - 7) x {fX / (15 + 17)} = 3.906 KHz 332 User's Manual U16504EE1V1UD00 Chapter 18 (2) Sound Generator Sound generator buzzer control register (SGBR) SGBR is a register that sets the basic frequency of the sound generator output signal. SGBR is set with an 8-bit memory manipulation instruction. RESET input clears SGBR to 00H. Figure 18-4 shows the SGBR format. Figure 18-4: Sound Generator Buzzer Control Register (SGBR) Format Symbol SGBR 7 0 6 0 5 0 4 0 3 2 1 0 Address After Reset R/W FFC2H 00H R/W SGBR3 SGBR2 SGBR1 SGBR0 SGBR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SGBR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SGBR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SGBR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Buzzer Output Frequency (KHz) Note fX = 8 MHz) 3.677 3.472 3.290 3.125 2.976 2.841 2.717 2.604 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 fX = 8.38 MHz) 3.851 3.637 3.446 3.273 3.117 2.976 2.847 2.728 2.619 2.518 2.425 2.339 2.258 2.182 2.112 2.046 Note: Output frequency where SGCL0, SGCL1, and SGCL2 are 0, 0, and 0. Cautions: 1. When rewriting SGBR to other data, stop the timer operation (TCE = 0) beforehand. 2. Bits 4 to 7 must be set to 0. (3) Sound generator amplitude register (SGAM) SGAM is a register that sets the amplitude of the sound generator output signal. SGAM is set with an 8-bit memory manipulation instruction. RESET input clears SGAM to 00H. Figure 18-5 shows the SGAM format. User's Manual U16504EE1V1UD00 333 Chapter 18 Figure 18-5: Sound Generator Sound Generator Amplitude Register (SGAM) Format Symbol SGAM 7 0 6 5 4 3 2 1 0 Address After Reset R/W FFC1H 00H R/W SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0 SGAM6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SGAM5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SGAM4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SGAM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 | 1 SGAM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SGAM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SGAM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Amplitude 0/128 2/128 3/128 4/128 5/128 6/128 7/128 8/128 9/128 10/128 11/128 12/128 13/128 14/128 15/128 16/128 17/128 18/128 19/128 20/128 21/128 22/128 23/128 24/128 25/128 26/128 27/128 28/128 29/128 30/128 31/128 | 128/128 Cautions: 1. When rewriting the contents of SGAM, the timer operation does not need to be stopped. However, note that a high level may be output for one period due to rewrite timing. 2. Bit 7 must be set to 0. 334 User's Manual U16504EE1V1UD00 Chapter 18 Sound Generator 18.4 Sound Generator Operations 18.4.1 To output basic cycle signal SGOF (without amplitude) Select SGOF output by setting bit 3 (SGOB) of the sound generator control register (SGCR) to "0". The basic cycle signal with a frequency specified by the SGCL0 to SGCL2 and SGBR0 to SGBR3 is output. At the same time, the amplitude signal with an amplitude specified by the SGAM0 to SGAM6 is output from the SGOA pin. Figure 18-6: Sound Generator Output Operation Timing n n n n n n Timer Comparator 1 coincidence SGOF SGOA User's Manual U16504EE1V1UD00 335 Chapter 18 Sound Generator 18.4.2 To output basic cycle signal SGO (with amplitude) Select SGO output by setting bit 3 (SGOB) of the sound generator control register (SGCR) to "1". The basic cycle signal with a frequency specified by the SGCL0 to SGCL2 and SGBR0 to SGBR3 is output. When SGO output is selected, the SGOA pin can be used as a PCL output (clock output) or I/O port pin. Figure 18-7: Sound Generator Output Operation Timing n n n n n n Timer Comparator 1 coincidence SGOF SGOA SGO 336 User's Manual U16504EE1V1UD00 Chapter 19 Meter Controller / Driver 19.1 Meter Controller/Driver Functions The meter controller/driver is a function to drive a stepping motor for external meter control or cross coil. * Can set pulse width with a precision of 8 bits * Can set pulse width with a precision of 8 + 1 bits with 1-bit addition function * Can drive up to four 360 type meters Figure 19-1 shows the block diagram of the meter controller/driver. Figure 19-2 shows 1-bit addition circuit block diagram. Figure 19-1: Meter Controller/Driver Block Diagram Internal Bus Timer mode control register (MCNTC) Port mode control register (PMC) PCS PCE MODn ENn fx fx/8 fx/16 fx/64 fx/128 fx/256 fx/512 TM52out Selector Selector fx/2 8-bit timer register fcc OVF MODn ENn S Q Output control circuit SMn1(sin+) SMn2(sin-) Compare register (MCMPn0) 1-bit addition circuit R MODn ENn S Q Compare register (MCMPn1) 1-bit addition circuit Output control circuit SMn3(cos+) SMn4(cos-) R 2 2 SMCL2 SMCL1 SMCL0 TENn ADBn1 ADBn0 DIRn1 DIRn0 Compare control register n (MCMPCn) Internal Bus Meter C/D clock selection (SMSWI) Remark: n = 1 to 4 The meter controller/driver is a peripheral to control/drive up to four external meters (stepper motor/ cross coil motors). User's Manual U16504EE1V1UD00 337 Chapter 19 Figure 19-2: Meter Controller / Driver 1-bit Addition Circuit Block Diagram OVF S Selector Q R Compare register (MCMPnm) fCC S Q 2 ADBn1 ADBn0 Compare control register (MCMPCn) Internal bus Remark: n = 1 to 4, m = 0, 1 19.2 Meter Controller/Driver Configuration The meter controller/driver consists of the following hardware. Table 19-1: Meter Controller/Driver Configuration Item Timer Register Control registers Pulse control circuit Configuration Free-running up counter (SMCNT): 1 channel Compare register (MCMPn1, MCMPn0): 8 channels Timer mode control register (MCNTC) Compare control register n (MCMPCn) Port mode control register (PMC) 1-bit addition circuit/output control circuit Remark: n = 1 to 4 338 User's Manual U16504EE1V1UD00 Chapter 19 (1) Free running up counter (SMCNT) Meter Controller / Driver MCNT is an 8-bit free running counter. It is also a register that executes an increment at the rising edge of the input clock. A PWM pulse with a resolution of 8 bits can be created. The duty factor can be set in a range of 0 to 100%. The count value is cleared in the following cases. * When RESET signal input * When counter stops (PCE = 0) (2) Compare register n0 (MCMPn0) MCMPn0 is an 8-bit register that can rewrite a complete value according to the specification by bit 4 (TENn) of the compare control register n (MCMPCn). The values of these registers are cleared to 00H at RESET. The hardware is cleared to 0 by RESET. MCMPn0 is a register that supports read/write only for 8-bit access instructions. MCMPn0 continuously compares its value with the SMCNT value. When the two values match, a match signal on the sin side of the meter n is generated. (3) Compare register n1 (MCMPn1) MCMPn1 is an 8-bit register that can rewrite compare values through specification of bit 4 (TENn) of Compare control register n (MCMPCn). RESET input sets this register to 00H and clears hardware to 0. MCMPn1 is a register that supports read/write only for 8-bit access instructions. MCMPn1 compares its value with the SMCNT value. When the two values match, a match signal on cos side of the meter n is generated. (4) 1-bit addition circuit The 1-bit addition circuit repeats 1-bit addition/non-addition to the PWM output alternately upon MCNT overflow, and enables the state of the PWM output between the current compare value and the next compare value. This circuit is controlled by bits 2 and 3 (ADBn0, ADBn1) of the MCMPCn register. User's Manual U16504EE1V1UD00 339 Chapter 19 (5) Output control circuit Meter Controller / Driver This circuit consists of a Pch and Nch drivers and can drive a meter in H bridge configuration by connecting a coil. When a meter is driven in half bridge configuration, the unused pins can be used as normal output port pins. The relation of the duty factor of the PWM signal output from the SMnm pin is indicated by the following expression (n = 1 to 4, m = 0, 1). PWM (duty) = Set value of MCMPnm x cycle of MCNT count clock 255 x cycle of MCNT count clock x 100% = Set value of MCMPnm 255 x 100% Cautions: 1. MCMPn0 and MCMPn1 cannot be read or written by a 16-bit access instruction. 2. MCMPn0 and MCMPn1 are in master-slave configuration, and SMCNT is compared with a slave register. The PWM pulse is not generated until the first overflow occurs after the counting operation has been started because the compare data is not transferred to the slave. (6) Meter Controller/Driver Clock Switch The input clock of the meter controller/driver can be selected with the meter controller/driver clock switch. By default the register is set to 00H of RESET. SMSWI is a register that supports read/write only as 8-bit instruction. 340 User's Manual U16504EE1V1UD00 Chapter 19 Meter Controller / Driver 19.3 Meter Controller/Driver Control Registers The meter controller/driver is controlled by the following three registers. * Timer mode control register (MCNTC) * Compare control register n (MCMPCn) * Port mode control register (PMC) Remark: n = 1 to 4 (1) Timer mode control register (MCNTC) MCNTC is an 8-bit register that controls the operation of the free-running up counter (SMCNT). MCNTC is set with an 8-bit memory manipulation instruction. RESET input clears MCNTC to 00H. Figure 19-3 shows the MCNTC format. Figure 19-3: Timer Mode Control Register (MCNTC) Format Symbol MCNTC 7 0 6 0 5 PCS 4 PCE 3 0 2 0 1 0 0 0 Address After Reset R/W FFBFH 00H R/W PCS 0 1 Timer Counter Clock Selection Selection via SMSWI register fX/2 PCE 0 1 Timer Operation Control Operation stopped (timer value is cleared) Operation enabled Cautions: 1. When rewriting MCNTC to other data, stop the timer operation (PCE=0) beforehand. 2. Bits 0 to 3, 6, and 7 must be set to 0. User's Manual U16504EE1V1UD00 341 Chapter 19 (2) Compare control register (MCMPCn) Meter Controller / Driver MCMPCn is an 8-bit register that controls the operation of the compare register and output direction of the PWM pin. MCMPCn is set with an 8-bit memory manipulation instruction. RESET input clears MCMPCn to 00H. Figure 19-4 shows the MCMPCn format. Figure 19-4: Compare Control Register n (MCMPCn) Format Symbol MCMPCn 7 0 6 0 5 0 4 TENn 3 ADBn1 2 ADBn0 1 DIRn1 0 DIRn0 Address After Reset R/W FFCCH to FFCFH 00H R/W TENn Note 0 1 Enables Transfer by Register from Master to Slave Disables data transfer from master to slave. New data can be written. Transfer data from master to slave when SMCNT overflows. New data cannot be written. ADBn1 0 1 Control of 1-bit Addition circuit (cos side of meter n) No 1-bit addition to PWM output 1-bit addition to PWM output ADBn0 0 1 Control of 1-bit Addition circuit (sin side of meter n) No 1-bit addition to PWM output 1-bit addition to PWM output Remark: n = 1 to 4 Note: TENn functions as a control bit and status flag. As soon as the timer overflows and PWM data is output, TENn is cleared to "0" by hardware. The relation among the DIRn1 and DIRn0 bits of the MCMPCn register and output pin is shown below. DIRn1 0 0 1 1 DIRn2 0 1 0 1 Direction Control Bit SMn1 PWM PWM 0 0 SMn2 0 0 PWM PWM SMn3 PWM 0 0 PWM SMn4 0 PWM PWM 0 Caution: Bits 5 to 7 must be set to 0. 342 User's Manual U16504EE1V1UD00 Chapter 19 (3) Port mode control register (PMC) Meter Controller / Driver PMC is an 8-bit register that specifies PWM/PORT output. PMC is set with an 8-bit memory manipulation instruction. RESET input clears PMC to 00H. Figure 19-5 shows the PMC format. Figure 19-5: Port Mode Control Register (PMC) Format (1/2) Symbol PMC 7 MOD4 6 MOD3 5 MOD2 4 MOD1 3 EN4 2 EN3 1 EN2 0 EN1 Address After Reset R/W FFCBH 00H R/W MOD4 0 1 Meter 4 Full/Half Bridge Selection Meter 4 output is full bridge Meter 4 output is half bridge MOD3 0 1 Meter 3 Full/Half Bridge Selection Meter 3 output is full bridge Meter 3 output is half bridge MOD2 0 1 Meter 2 Full/Half Bridge Selection Meter 2 output is full bridge Meter 2 output is half bridge MOD1 0 1 Meter 1 Full/Half Bridge Selection Meter 1 output is full bridge Meter 1 output is half bridge EN4 0 1 Meter 4 Port/PWM Mode Selection Meter 4 output is in port mode Meter 4 output is in PWM mode EN3 0 1 Meter 3 Port/PWM Mode Selection Meter 3 output is in port mode Meter 3 output is in PWM mode User's Manual U16504EE1V1UD00 343 Chapter 19 Figure 19-5: Meter Controller / Driver Port Mode Control Register (PMC) Format (2/2) EN2 0 1 Meter 2 Port/PWM Mode Selection Meter 2 output is in port mode Meter 2 output is in PWM mode EN1 0 1 Meter 1 Port/PWM Mode Selection Meter 1 output is in port mode Meter 1 output is in PWM mode The relation among the ENn and MODn bits of the PMC register, DIRn1 and DIRn0 bits of the MCMPCn register, and output pins is shown below. ENn 0 1 1 1 1 1 1 1 1 MODn X 0 0 0 0 1 1 1 1 DIRn1 X 0 0 1 1 0 0 1 1 DIRn0 X 0 1 0 1 0 1 0 1 SMn1 (sin +) PORT PWM PWM GND GND PWM PWM PORT PORT SMn2 (sin -) PORT GND GND PWM PWM PORT PORT PWM PWM SMn3 (cos +) PORT PWM GND GND PWM PWM PORT PORT PWM SMn4 (cos -) PORT GND PWM PWM GND PORT PWM PWM PORT Mode Port mode PWM mode full bridge PWM mode half bridge DIRn1 and DIRn0 address the quadrant of sin and cos. DIRn1 and DIRn0 = 00 through 11 correspond to quadrants 1 through 4, respectively. The PWM signal is routed to the specific pin with respect to the sin/cos of each quadrant. When ENn = 0, all the output pins are used as port pins regardless of MODn, DIRn1 and DIRn0. When ENn = 1 and MODn = 0, the full bridge mode is set, and 0 a pin that does not output a PWM signal is "0". When ENn = 1 and MODn = 1, the half bridge mode is set, and the pin that does not output a PWM signal is used as a port pin. Caution: The output polarity of the PWM output changes when SMCNT overflows. (4) Meter controller/driver clock register (SMSWI) SMSWI is an 8-bit register that specifies the input clock of the meter controller/driver. SMSWI is set with an 8-bit memory manipulation instruction. RESET input sets SMSWI to 00H. Figure 19-6 shows the SMSWI format. 344 User's Manual U16504EE1V1UD00 Chapter 19 Figure 19-6: Meter Controller / Driver Meter Controller/Driver Clock Register (SMSWI) Format Symbol SMSWI 7 0 6 0 5 0 4 0 3 0 2 1 0 Address After Reset R/W FFBDH 00H R/W SMCL2 SMCL1 SMCL0 SMCL2 0 0 0 0 1 1 1 1 SMCL1 0 0 1 1 0 0 1 1 SMCL0 0 1 0 1 0 1 0 1 Meter Controller/Driver Clock Switch fX fX/8 fX/16 fX/64 fX/128 fX/256 fX/512 TM52 Output User's Manual U16504EE1V1UD00 345 Chapter 19 Meter Controller / Driver 19.4 Meter Controller/Driver Operations 19.4.1 Basic operation of free-running up counter (SMCNT) The free-running up counter is clocked by the count clock selected by the PCS bit of the time mode control register. The value of SMCNT is cleared by RESET input. The counting operation is enabled or disabled by the PCE bit of the timer mode control register (MCNTC). Figure 19-7 shows the timing from count start to restart. Figure 19-7: Restart Timing after Count Stop (Count Start Count Stop Count Start) CLK MCNT 0H 1H 2H N N+1 00H 1H 2H 3H 4H PCE Count Start Count Stop Count Start Remark: N = 00H to FFH 346 User's Manual U16504EE1V1UD00 Chapter 19 19.4.2 Update of PWM data Meter Controller / Driver Confirm that bit 4 (TENn) of MCMPCn is 0, wait for more than one PWM clock cycle (as selected in SMSWI register), and then write 8-bit PWM data to MCMPn1, MCMPn, and ADBn1 and ADBn0 of MCMPCn. At the same time, set TENn to 1. The data will be automatically transferred to the slave latch when the timer overflows, and the PWM data becomes valid. At the same time, TENn is automatically cleared to 0. Figure 19-8: Update of PWM data TENn = 0 ? No Yes Wait > 1 PWM clock cycle While MCMPCn data TENn = 1 User's Manual U16504EE1V1UD00 347 Chapter 19 19.4.3 Operation of 1-bit addition circuit Meter Controller / Driver Figure 19-9: Timing in 1-bit Addition Circuit Operation FFH SMCNT Value 00H N 01H OVF (Overflow) Match signal of expected value N PWM output of expected value N (1-bit non-addition) PWM output of expected value N (1-bit addition) PWM output of expected value N+1 (1-bit non-addition) The 1-bit addition mode repeats 1-bit addition/non-addition to the PWM output every second SMCNT overflow. Therefore, the falling edge of the PWM output signal will occur at compare value N and compare value N+1 alternately. A 1-bit addition to the PWM output is applied by setting ADBn of the MCMPCn register to 1. In 1-bit non-addition mode the falling edge of the PWM output signal will always occur at compare value N+1 of SMCNT. A 1-bit non-addition (normal output) is applied by setting ADBn to 0. Remark: n = 1 to 4 348 User's Manual U16504EE1V1UD00 Chapter 19 Meter Controller / Driver 19.4.4 PWM output operation (output with 1 clock shifted) Figure 19-10: Count clock Timing of Output with 1 Clock Shifted Meter 1 sin (SM11, SM12) Meter 1 cos (SM13, SM14) Meter 2 sin (SM21, SM22) Meter 2 cos (SM23, SM24) Meter 3 sin (SM31, SM32) Meter 3 cos (SM33, SM34) Meter 4 sin (SM41, SM42) Meter 4 cos (SM43, SM44) If the wave of sin and cos of meters 1 to 4 rises and falls internally as indicated by the broken line, the SM11 to SM44 pins always shift the count clock by 1 clock. The output signals are generated in order to prevent VDD/GND from fluctuating. User's Manual U16504EE1V1UD00 349 [MEMO] 350 User's Manual U16504EE1V1UD00 Chapter 20 20.1 Interrupt Function Types Interrupt Functions The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal. The non-maskable interrupt has one source of interrupt request from the watchdog timer. (2) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register (PR0L, PR0H, and PR1L). Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same priority are simultaneously generated, each interrupts has a predetermined priority (see Table 20-1, "Interrupt Source List," on page 352). A standby release signal is generated. The maskable interrupt has seven sources of external interrupt requests and fifteen sources of internal interrupt requests. (3) Software interrupt This is a vectored interrupt to be generated by executing the BRK instruction. It is acknowledged even in a disabled state. The software interrupt does not undergo interrupt priority control. User's Manual U16504EE1V1UD00 351 Chapter 20 Interrupt Functions 20.2 Interrupt Sources and Configuration There are total of 24 interrupt sources: non-maskable, maskable, and software interrupts. Table 20-1: Maskability Nonmaskable Interrupt Priority Note 1 Interrupt Source List Basic Internal/ Vector Structure External Address TypeNote 2 (A) 0004H Interrupt Source Name INTWDT INTWDT INTAD INTOVF INTTM20 INTTM21 INTTM22 INTP0 INTP1 INTP2 INTCE INTCR INTCT0 INTCT1 CAN Error CAN Receive CAN Transmit buffer 0 CAN Transmit buffer 1 Pin input edge detection Trigger Overflow of watchdog timer (When the Watchdog timer NMI is selected) Overflow of watchdog timer (When the interval timer mode is selected) End of A/D converter conversion Overflow of 16-bit timer 2 Generation of 16-bit timer capture register (CR20) match signal Generation of 16-bit timer capture register (CR21) match signal Generation of 16-bit timer capture register (CR22) match signal _ 0 1 2 3 4 5 6 7 8 9 0006H Internal 0008H 000AH 000CH 000EH 0010H External 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H Internal 0024H 0026H 0028H 002AH 002EH 0030H 0032H Internal 003EH (D) (B) (C) (B) Maskable 10 11 12 13 14 15 16 17 18 19 20 21 22 INTCSI30 End of serial interface channel 30 (SIO30)transfer INTSER0 Channel 1 UART reception error generation INTSR0 INTST0 End of channel 1 UART reception End of channel 1 UART transfer Generation of 8-bit timer/event counter 50 match INTTM50 signal INTTM51 Generation of 8-bit timer/event counter 51 match signal INTTM52 Generation of 8-bit timer 52 match signal 002AH INTWTI INTWT Reference time interval signal from watch timer Reference time interval signal from watch timer INTCSI31 End of serial interface channel 31 (SIO31) transfer BRK BRK instruction execution Software _ Notes: 1. Default priorities are intended for two or more simultaneously generated maskable interrupt requests. 0 is the highest priority and 22 is the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) of Figure 20-1on page 353. 352 User's Manual U16504EE1V1UD00 Chapter 20 Figure 20-1: Interrupt Functions Basic Configuration of Interrupt Function (1/2) (a) Internal non-maskable interrupt Internal Bus Interrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal (b) Internal maskable interrupt Internal Bus MK IE PR ISP Interrupt Request IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Remark: IF IE ISP MK PR : : : : : Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specify flag User's Manual U16504EE1V1UD00 353 Chapter 20 Interrupt Functions Figure 20-1: Basic Configuration of Interrupt Function (2/2) (c) External maskable interrupt (except INTP0) Internal Bus External Interrupt Mode Register (EGN, EGP) MK IE PR ISP Interrupt Request Edge Detector IF Priority Control Circuit Vector Table Address Generator Standby Release Signal (d) Software interrupt Internal Bus Interrupt Request Priority Control Circuit Vector Table Address Generator Remark: IF IE ISP MK PR : : : : : Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specify flag 354 User's Manual U16504EE1V1UD00 Chapter 20 Interrupt Functions 20.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L) * Interrupt mask flag register (MK0L, MK0H, MK1L) * Priority specify flag register (PR0L, PR0H, PR1L) * External interrupt mode register (EGP, EGN) * Program status word (PSW) Table 20-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding to interrupt request sources. Table 20-2: Various Flags Corresponding to Interrupt Request Sources Interrupt Request Flag PIF0 PIF1 PIF2 OVFIF TMIF20 TMIF21 TMIF22 TMIF50 TMIF51 TMIF52 WTIIF WTIF WDTIF ADIF CSIIF30 SERIF0 SRIF0 STIF0 CEIF RRF CTIF0 CTIF1 WEIF CSIIF31 Interrupt Mask Flag PMK0 PMK1 PMK2 OVFMK TMMK20 TMMK21 TMMK22 TMMK50 TMMK51 TMMK52 WTIMK WTMK WDTMK ADMK CSIMK30 SERMK0 SRMK0 STMK0 CEMK CRMK CTMK0 CTMK1 WEMK CSIMK31 Priority Specify Flag PPR0 PPR1 PPR2 OVFPR TMPR20 TMPR21 TMPR22 TMPR50 TMPR51 TMPR52 WTIPR WTPR WDTPR ADPR CSIPR30 SERPR0 SRPR0 STPR0 CEPR CRPR CTPR0 CTPR1 WEPR CSIPR31 Interrupt Request Signal Name INTP0 INTP1 INTP2 INTOVF INTTM20 INTTM21 INTTM22 INTM50 INTM51 INTM52 INTWTI INTWT INTWDT INTAD INTCSI30 INTSER0 INTSR0 INTST0 INTCE INTCR INTCT0 INTCT1 INTWE INTCSI31 User's Manual U16504EE1V1UD00 355 Chapter 20 Interrupt Functions (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register IF0, use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to 00H. Figure 20-2: Interrupt Request Flag Register Format Symbol IF0L IF0H IF1L <7> PIF1 <6> PIF0 <5> <4> <3> <2> <1> ADIF CEIF <0> WDTIF PIF2 STIF0 Address After Reset R/W FFE0H FFE1H FFE2H 00H 00H 00H R/W R/W R/W TMIF22 TMIF21 TMIF20 OVFIF CTIF0 CRIF SRIF0 SERIF0 CSIIF30 CTIF1 CSIIF31 WTIF WTIIF 0 TMIF52 TMIF51 TMIF50 xxIFx 0 1 Interrupt request flag No interrupt request signal Interrupt request signal is generated; interrupt request state Cautions: 1. WDTIF flag is R/W enabled only when the watchdog timer is used as an interval timer. If used in the watchdog timer mode 1, set WDTIF flag to 0. 2. Set always 0 in IF1L bit 4. 356 User's Manual U16504EE1V1UD00 Chapter 20 (2) Interrupt Functions Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to FFH. Figure 20-3: Interrupt Mask Flag Register Format Symbol MK0L <7> PMK1 <6> PMK0 <5> <4> <3> <2> <1> <0> Address After Reset R/W FFE4H FFE5H FFE6H FFH FFH FFH R/W R/W R/W TMMK22 TMMK21 TMMK20 OVFMK ADMK WDTMK CRMK CEMK PMK2 MK0H SRMK0 SERMK0 CSIMK30 CTMK1 CTMK0 MK1L CSIMK31 WTMK WTIMK 1 TMMK52 TMMK51 TMMK50 STMK0 xxMKx 0 1 Interrupt Servicing Control Interrupt servicing enabled Interrupt servicing disabled Cautions: 1. If WDTMK flag is read when the watchdog timer is used as a non-maskable interrupt, WDTMK value becomes undefined. 2. Set always 1 in MK1L bit 4. User's Manual U16504EE1V1UD00 357 Chapter 20 Interrupt Functions (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to FFH. Figure 20-4: Priority Specify Flag Register Format Symbol PR0L PR0H <7> PPR1 <6> <5> <4> <3> <2> <1> <0> Address After Reset R/W FFE8H FFE9H FFEAH FFH FFH FFH R/W R/W R/W PPR0 TMPR22 TMPR21 TMPR20 OVFPR CRPR ADPR WDTPR CEPR PPR2 SRPR0 SERPR0 CSIPR30 CTPR1 CTPR0 WTIPR 1 PR1L CSIPR31 WTPR TMPR52 TMPR51 TMPR50 STPR0 xxPRx 0 1 High priority level Low priority level Priority Level Selection Cautions: 1. The WDTPR flag is only valid, if the watchdog timer is used as interval timer. If the non-maskable interrupt of the watchdog timer is used, set WDTPR to 1. 2. Set always 1 in PR1L bit 4. 358 User's Manual U16504EE1V1UD00 Chapter 20 (4) Interrupt Functions External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) EGP and EGN specify the valid edge to be detected on pins P00 to P02. EGP and EGN can be read or written to with a 1-bit or 8-bit memory manipulation instruction. These registers are set to 00H when the RESET signal is output. Figure 20-5: Formats of External Interrupt Rising Edge Enable Register and External Interrupt Falling Edge Enable Register Symbol EGP Symbol EGN 7 0 7 0 6 0 6 0 5 0 5 0 4 0 4 0 3 0 3 0 2 EGP2 2 EGN2 1 EGP1 1 EGN1 0 EGP0 0 EGN0 Address After Reset R/W FF48H 00H R/W Address After Reset R/W FF49H 00H R/W EGPn 0 0 1 1 EGNn 0 1 0 1 Valid edge of INTPn pin (n = 0 - 2) Interrupt disable Falling edge Rising edge Both rising and falling edges User's Manual U16504EE1V1UD00 359 Chapter 20 Interrupt Functions (5) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupts (enable/disable) and the ISP flag to control multiple interrupt servicing are mapped. Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, and when the BRK instruction is executed, the contents of PSW automatically is saved onto the stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag. The acknowledged contents of PSW is also saved onto the stack with the PUSH PSW instruction. It is retrieved from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets PSW to 02H. Figure 20-6: Program Status Word Format Symbol PSW 7 IE 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY After Reset R/W 02H R/W ISP 0 1 Priority of Interrupt Currently Being Received High-priority interrupt servicing (low-priority interrupt disable) Interrupt request not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) IE 0 1 Interrupt Request Acknowledge Enable/Disable Disable Enable 360 User's Manual U16504EE1V1UD00 Chapter 20 Interrupt Functions 20.4 Interrupt Servicing Operations 20.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, PSW and PC are pushed on the stack. The IE and ISP flags are reset to 0, and the vector table contents are loaded into PC. A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request is generated twice or more during a non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. Figure 20-7: Flowchart from Non-Maskable Interrupt Generation to Acknowledge Start WDT = 1 (with watchdog timer mode selected)? No Interval timer Yes Overflow in WDT? No Yes WDT = 0 (with non-maskable interrupt selected)? No Reset processing Yes Interrupt request generation WDT interrupt servicing? No Interrupt request held pending Yes Interrupt control register unaccessed? No Yes Interrupt service start Remark: WDTM : WDT : Watchdog timer mode register Watchdog timer User's Manual U16504EE1V1UD00 361 Chapter 20 Interrupt Functions Figure 20-8: Non-Maskable Interrupt Request Acknowledge Timing PSW and PC Save, Jump Interrupt Sevicing to Interrupt Servicing Program CPU Instruction Instruction Instruction WDTIF Remark: WDTIF : Watchdog timer interrupt request flag Figure 20-9: Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request 1 Instruction Execution NMI Request NMI Request Reserve Reserved NMI Request Processing (b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main Routine NMI Request NMI Request 1 Instruction Execution NMI Request Reserved Reserved Although two or more NMI requests have been generated, only one request has been acknowledged. 362 User's Manual U16504EE1V1UD00 Chapter 20 Interrupt Functions 20.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with ISP flag reset to 0). Wait times from maskable interrupt request generation to interrupt servicing are as follows. Table 20-3: Times from Maskable Interrupt Request Generation to Interrupt Service Minimum Time When xxPRx = 0 When xxPRx = 1 7 clocks 8 clocks Maximum TimeNote 32 clocks 33 clocks Note: If an interrupt request is generated just before a divide instruction, the wait time is maximized. Remark: 1 clock: 1/ fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is acknowledged first. If two or more requests are specified for the same priority with the priority specify flag, the interrupt request with the higher default priority is acknowledged first. Any reserved interrupt requests are acknowledged when they become acknowledgeable. Figure 20-10 on page 364 shows interrupt request acknowledge algorithms. When a maskable interrupt request is acknowledged, the contents of program status word (PSW) and program counter (PC) are saved in this order onto the stack. Then, the IE flag is reset (to 0), and the value of the acknowledged interrupt priority specify flag is transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded into PC and the program will branch accordingly. Return from the interrupt is possible with the RETI instruction. User's Manual U16504EE1V1UD00 363 Chapter 20 Interrupt Functions Figure 20-10: Interrupt Request Acknowledge Processing Algorithm Start No xxIF = 1? Yes (Interrupt Request Generation) No xxMK = 0? Yes Interrupt request reserve Yes (High priority) xxPR = 0? No (Low Priority) Yes Any highpriority interrupt among simultaneously generated xxPR = 0 interrupts? Interrupt request reserve Any simultaneously generated xxPR = 0 interrupts? No Yes Interrupt request reserve No No IE = 1? Yes Vectored interrupt servicing Any simultaneously generated high-priority interrupts? No Yes Interrupt request reserve Interrupt request reserve IE = 1? Yes No Interrupt request reserve ISP = 1? Yes Vectored interrupt servicing No Interrupt request reserve Remark: xxIF : Interrupt request flag xxMK : Interrupt mask flag xxPR : Priority specify flag IE : Flag to control maskable interrupt request acknowledge ISP : Flag to indicate the priority of interrupt being serviced (0 = an interrupt with higher priority is being serviced, 1 = interrupt request is not acknowledged or an interrupt with lower priority is being serviced) 364 User's Manual U16504EE1V1UD00 Chapter 20 Figure 20-11: Interrupt Functions Interrupt Request Acknowledge Timing (Minimum Time) 6 Clocks PSW and PC Save, Jump to Interrupt Servicing Interrupt Servicing Program CPU Processing Instruction Instruction xxIF (xxPR = 1) 8 Clocks xxIF (xxPR = 0) 7 Clocks Remark: 1 clock: 1/ fCPU (fCPU: CPU clock) Figure 20-12: Interrupt Request Acknowledge Timing (Maximum Time) 25 Clocks 6 Clocks PSW and PC Save, Jump to Interrupt Servicing Interrupt Servicing Program CPU Processing Instruction Divide Instruction xxIF (xxPR = 1) 33 Clocks xxIF (xxPR = 0) 32 Clocks Remark: 1 clock: 1/ fCPU (fCPU: CPU clock) User's Manual U16504EE1V1UD00 365 Chapter 20 Interrupt Functions 20.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled. If a software interrupt is acknowledged, the contents of program status word (PSW) and program counter (PC) are saved to stacks, in this order. Then the IE flag is reset (to 0), and the contents of the vector tables (003EH and 003FH) are loaded into PC and the program branches accordingly. Return from the software interrupt is possible with the RETB instruction. Caution: Do not use the RETI instruction for returning from the software interrupt. 20.4.4 Multiple interrupt servicing A multiple interrupt service consists in acknowledging another interrupt during the execution of another interrupt routine. A multiple interrupt service is generated only in the interrupt request acknowledge enable state (IE = 1) (except non-maskable interrupt). As soon as an interrupt request is acknowledged, it enters the acknowledge disable state (IE = 0). Therefore, in order to enable multiple interrupts, it is necessary to set the interrupt enable state by setting the IE flag (1) with the EI instruction during interrupt servicing. Even in an interrupt enabled state, a multiple interrupt may not be enabled. However, it is controlled according to the interrupt priority. There are two priorities, the default priority and the programmable priority. The multiple interrupt is controlled by the programmable priority control. If an interrupt request with the same or higher priority than that of the interrupt being serviced is generated, it is acknowledged as a multiple interrupt. In the case of an interrupt with a priority lower than that of the interrupt being processed, it is not acknowledged as a multiple interrupt. An interrupt request not acknowledged as a multiple interrupt due to interrupt disable or a low priority is reserved and acknowledged following one instruction execution of the main processing after the completion of the interrupt being serviced. During non-maskable interrupt servicing, multiple interrupts are not enabled. Table 20-4 on page 367 shows an interrupt request enabled for multiple interrupt during interrupt servicing, and Figure 20-13 on page 368 shows multiple interrupt examples. 366 User's Manual U16504EE1V1UD00 Chapter 20 Interrupt Functions Table 20-4: Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Maskable Interrupt Request xxPR = 0 IE = 1 D E E E IE = 0 D D D D xxPR = 1 IE = 1 D D E E IE = 0 D D D D Maskable Interrupt Non-maskable Request Interrupt Request Interrupt being serviced Non-maskable interrupt ISP = 0 Maskable Interrupt ISP = 1 Software interrupt E E D E Remarks: 1. E : Multiple interrupt enable 2. D : Multiple interrupt disable 3. ISP and IE are the flags contained in PSW ISP = 0 : An interrupt with higher priority is being serviced ISP = 1 : An interrupt request is not accepted or an interrupt with lower priority is being serviced IE = 0 : Interrupt request acknowledge is disabled IE = 1 : Interrupt request acknowledge is enabled 4. xxPR is a flag contained in PR0L, PR0H, and PRIL xxPR = 0 : Higher priority level xxPR = 1 : Lower priority level User's Manual U16504EE1V1UD00 367 Chapter 20 Interrupt Functions Figure 20-13: Multiple Interrupt Example (1/2) (a) Example 1. Two multiple interrupts generated Main Processing INTxx Servicing IE = 0 EI EI INTyy (PR = 0) INTzz (PR = 0) RETI RETI IE = 0 EI INTyy Servicing IE = 0 INTzz Servicing INTxx (PR = 1) RETI During interrupt INTxx servicing, two interrupt requests, INTyy and INTzz are acknowledged, and a multiple interrupt is generated. An EI instruction is issued before each interrupt request acknowledge, and the interrupt request acknowledge enable state is set. (b) Example 2. Multiple interrupt is not generated by priority control Main Processing INTxx Servicing INTyy Servicing EI IE = 0 EI INTyy (PR = 1) RETI INTxx (PR = 0) 1 Instruction Execution IE = 0 RETI The interrupt request INTyy generated during interrupt INTxx servicing is not acknowledged because the interrupt priority is lower than that of INTxx, and a multiple interrupt is not generated. INTyy request is retained and acknowledged after execution of 1 instruction execution of the main processing. Remark: PR = 0 : Higher priority level PR = 1 : Lower priority level IE = 0 : Interrupt request acknowledge disable 368 User's Manual U16504EE1V1UD00 Chapter 20 Figure 20-13: Interrupt Functions Multiple Interrupt Example (2/2) (c) Example 3. A multiple interrupt is not generated because interrupts are not enabled Main Processing INTxx Servicing IE = 0 INTyy (PR = 0) RETI INTyy Servicing EI INTxx (PR = 0) 1 Instruction Execution IE = 0 RETI Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request INTyy is not acknowledged, and a multiple interrupt is not generated. The INTyy request is reserved and acknowledged after 1 instruction execution of the main processing. Remark: PR = 0 : Higher priority level IE = 0 : Interrupt request acknowledge disable User's Manual U16504EE1V1UD00 369 Chapter 20 Interrupt Functions 20.4.5 Interrupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interrupt request is generated during the execution. The following list shows such instructions (interrupt request reserve instruction). * MOV * MOV * MOV * MOV1 * MOV1 * AND1 * OR1 * XOR * RETB * RETI * PUSH * POP * BT * BF * BTCLR * EI * DI * Manipulate instructions: for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, EGP, EGN PSW PSW PSW.bit, $addr16 PSW.bit, $addr16 PSW.bit, $addr16 PSW, #byte A, PSW PSW, A PSW.bit, CY CY, PSW.bit CY, PSW.bit CY, PSW.bit CY, PSW.bit * SET1/CLR1 PSW.bit Caution: BRK instruction is not an interrupt request reserve instruction described above. However, in a software interrupt started by the execution of BRK instruction, the IE flag is cleared to 0. Therefore, interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the BRK instruction. However, non-maskable interrupt requests are acknowledged. 370 User's Manual U16504EE1V1UD00 Chapter 20 Interrupt Functions Figure 20-14 shows the interrupt request hold timing. Figure 20-14: Interrupt Request Hold Save PSW and PC, Jump to interrupt service Interrupt service program CPU processing Instruction N Instruction M xxIF Remarks: 1. Instruction N: Instruction that holds interrupts requests 2. Instruction M: Instructions other than interrupt request pending instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request). User's Manual U16504EE1V1UD00 371 [MEMO] 372 User's Manual U16504EE1V1UD00 Chapter 21 Standby Function 21.1 Standby Function and Configuration 21.1.1 Standby function The standby function is designed to decrease the power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as much as in the STOP mode. The HALT mode is capable of restart immediately upon interrupt request and to carry out intermittent operations such as watch applications. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops and the whole system stops. CPU current consumption can be considerably decreased. Data memory low-voltage hold is possible. Thus, the STOP mode is effective to hold data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. However, because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request. In any mode, all the contents of the register, flag, and data memory just before entering the standby mode are held. The input/output port output latch and output buffer status are also held. Cautions: 1. When proceeding to the STOP mode, be sure to stop the peripheral hardware operation and execute the STOP instruction afterwards. 2. The following sequence is recommended for power consumption reduction of the A/D converter when the standby function is used: first clear bit 7 (ADCS1) of ADM1 to 0 to stop the A/D conversion operation, and then execute the HALT or STOP Instruction. User's Manual U16504EE1V1UD00 373 Chapter 21 21.1.2 Standby function control register Standby Function A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, it takes 217/fX until the STOP mode is cleared by RESET input. Figure 21-1: Oscillation Stabilization Time Select Register Format Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 1 0 Address After Reset R/W FFFAH 04H R/W OSTS2 OSTS1 OSTS0 OSTS2 0 0 0 1 1 OSTS1 0 0 1 1 0 OSTS0 0 1 0 1 0 Selection of Oscillation Stabilization Time when STOP Mode is Released 212/fX (512 s) 214/fX (2 ms) 215/fX (4.1 ms) 216/fX (8.9 ms) 217/fX (16.38 ms) Setting prohibited Other than above Caution: The wait time after STOP mode clear does not include the time (see "a" in the Figure 21-2 below) from STOP mode clear to clock oscillation start, regardless of clearance by RESET input or by interrupt generation. Figure 21-2: Standby Timing STOP Mode Clear X1 Pin Voltage Waveform a VSS Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operating at fX = 8.00 MHz 374 User's Manual U16504EE1V1UD00 Chapter 21 Standby Function 21.2 Standby Function Operations 21.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Table 21-1: HALT Mode Operating Status HALT mode setting HALT execution during main system clock operation Item Clock generator CPU Port (output latch) 16-bit timer (TM2) Main clock is oscillating / Clock supply to the CPU stops Operation stops Status before HALT mode setting is held Operable 8-bit timer event counter (TM50/TM51/TM52) Operable Watch timer Watchdog timer A/D converter Serial I/F (SIO30, SIO31) Serial I/F (UART) CAN Sound generator External interrupt (INTP0 to INTP2) LCD - C/D Meter - C/D Operable Operable Operation stops Operable Operable Operation stops Operable Operable Operable Operable User's Manual U16504EE1V1UD00 375 Chapter 21 (2) HALT mode clear Standby Function The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next address instruction is executed. Figure 21-3: HALT Mode Clear upon Interrupt Generation HALT Instruction Standby Release Signal Operating Mode Wait HALT Mode Oscillation Wait Operating Mode Clock Remarks: 1. The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. 2. Wait time will be as follows: * * When vectored interrupt service is carried out : 8 to 9 clocks When vectored interrupt service is not carried out : 2to 3 clocks (b) Clear upon non-maskable interrupt request The HALT mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled. 376 User's Manual U16504EE1V1UD00 Chapter 21 (c) Clear upon RESET input Standby Function As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 21-4: HALT Mode Release by RESET Input Wait 17 (2 /f x : 16.38 ms) HALT Instruction RESET Signal Reset Period Oscillation stop Operating Mode Clock HALT Mode Oscillation Oscillation Stabilization Wait Status Oscillation Operating Mode Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation at fX = 8.0 MHz Table 21-2: Release Source MKxx 0 0 0 Maskable interrupt request 0 0 1 Non-maskable interrupt request RESET input - Operation after HALT Mode Release PRxx 0 0 1 1 1 x IE 0 1 0 x 1 x x x ISP x x 1 Next address instruction execution 0 1 x x x Interrupt service execution HALT mode hold Interrupt service execution Reset processing Operation Next address instruction execution Interrupt service execution Remark: x: Don't care User's Manual U16504EE1V1UD00 377 Chapter 21 21.2.2 STOP mode (1) STOP mode set and operating status Standby Function The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions: 1. When the STOP mode is set, the X2 pin is internally connected to VDD via a pullup resistor to minimize leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock. 2. If there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait time set using the oscillation stabilization time select register (OSTS), the operating mode is set. The operating status in the STOP mode is described below. Table 21-3: STOP Mode Operating Status STOP execution during main system clock operation Main system clock stops oscillation Operation stops Status before STOP mode setting is held Operation stops Operable when TI50 or TI51 are selected as count clock Operation stops Operation stops Operation stops Operation stops Operable at external SCK Operation stops Operation stops Operation stops Operable Operation stops Operation stops STOP mode setting Item Clock generator CPU Port (output latch) 16-bit timer (TM2) 8-bit timer/event counter (TM50, TM51) 8-bit timer (TM52) Watch timer Watchdog timer A/D converter Serial I/F (SIO30, SIO31) Serial I/F (UART) CAN Sound generator External interrupt (INTP0 to INTP2) LCD - C/D Meter - C/D 378 User's Manual U16504EE1V1UD00 Chapter 21 (2) STOP mode release Standby Function The STOP mode can be cleared with the following three types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt acknowledge is disabled, the next address instruction is executed. Figure 21-5: STOP Mode Release by Interrupt Generation Wait (Time set by OSTS) STOP Instruction Standby Release Signal Operating Mode Oscillation STOP Mode Oscillation Stop Oscillation Stabilization Wait Status Oscillation Operating Mode Clock Remark: The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. User's Manual U16504EE1V1UD00 379 Chapter 21 (b) Release by RESET input Standby Function The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 21-6: Release by STOP Mode RESET Input Wait (2 17 /f x : 16.38 ms) STOP Instruction RESET Signal Operating Mode Oscillation Reset Period STOP Mode Oscillation Stop Oscillation Stabilization Wait Status Oscillation Operating Mode Clock Remarks: 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation at fX = 8.0 MHz Table 21-4: Release Source MKxx 0 0 0 Maskable interrupt request 0 0 1 RESET input - Operation after STOP Mode Release PRxx 0 0 1 1 1 x IE 0 1 0 x 1 x x ISP x x 1 Next address instruction execution 0 1 x x Interrupt service execution STOP mode hold Reset processing Operation Next address instruction execution Interrupt service execution Remark: x: Don't care 380 User's Manual U16504EE1V1UD00 Chapter 22 Reset Function 22.1 Reset Function The following two operations are available to generate the reset signal. * External reset input with RESET pin * Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in Table 23-1. Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. When a high level is input to the RESET input, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (217/fX). The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (217/fX) (see Figure 22-2, "Timing of Reset Input by RESET Input," on page 382, Figure 22-3, "Timing of Reset due to Watchdog Timer Overflow," on page 382, and Figure 22-4, "Timing of Reset Input in STOP Mode by RESET Input," on page 383). Cautions: 1. For an external reset, apply a low level for 10 s or more to the RESET pin. 2. During reset the main system clock oscillation remains stopped but the subsystem clock oscillation continues. 3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset. However, the port pin becomes high-impedance. Figure 22-1: Block Diagram of Reset Function RESET Reset Control Circuit Reset Signal Overflow Count Clock Watchdog Timer Stop Interrupt Function User's Manual U16504EE1V1UD00 381 Chapter 22 Reset Function Figure 22-2: Timing of Reset Input by RESET Input X1 Oscillation Stabilization Time Wait Normal Operation Reset Period (Oscillation Stop) Normal Operation (Reset Processing) RESET Internal Reset Signal Delay Delay High Impedance Port Pin Figure 22-3: Timing of Reset due to Watchdog Timer Overflow X1 Oscillation Stabilization Time Wait Normal Operation Reset Period (Oscillation Stop) Normal Operation (Reset Processing) Watchdog Timer Overflow Internal Reset Signal High Impedance Port Pin 382 User's Manual U16504EE1V1UD00 Chapter 22 Figure 22-4: Reset Function Timing of Reset Input in STOP Mode by RESET Input X1 STOP Instruction Execution Normal Operation Stop Status (Oscillation Stop) Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation (Reset Processing) RESET Internal Reset Signal Delay Delay Port Pin High Impedance Table 22-1: Hardware Program counter (PC)Note 1 Stack pointer (SP) Program status word (PSW) Hardware Status after Reset (1/3) Status after Reset The contents of reset vector tables (0000H and 0001H) are set Undefined 02H Data memory RAM General register LCD Display Data Memory Port (Output latch) Ports 0, 2, 3, 4, 5, 6, 8, 9 (P0, P2, P3, P4, P5,P6, P8, P9) UndefinedNote 2 UndefinedNote 2 Note 4 00H FFH 00H 00H 04H CFH Note 3 Port mode register (PM0, PM2, PM3, PM4, PM5, PM6, PM8, PM9) Pull-up resistor option register (PU0, PU3, PU4, PU6, PU8, PU9) Port function selection (PF3, PF4, PF8, PF9) Processor clock control register (PCC) Memory size switching register (IMS) Internal expansion RAM size switching register (IXS) Oscillation stabilization time select register (OSTS) Timer register (TM2) 16-bit timer/event counter 2 04H 00H Capture control register (CR20, CR21, CR22) 00H Prescaler mode register (PRM2) Mode control register (TMC2) 00H 00H Notes: 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remains unchanged after reset. 2. The post-reset status is held in the standby mode. 3. The value after RESET depends on the product (see Table 23-4, "Values when the Internal Expansion RAM Size Switching Register is Reset," on page 389) 4. RESET clears the LCD Display Data Memory to 00H. User's Manual U16504EE1V1UD00 383 Chapter 22 Reset Function Table 22-1: Hardware Timer register (TM50, TM51, TM52) 8-bit timer/event counters 50, 51 and 52 Compare register (CR50, CR51, CR52) 00H 00H Hardware Status after Reset (2/3) Status after Reset Clock select register (TCL50, TCL51, TCL52) 00H Mode control register (TMC50, TMC51, TMC52) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Watch timer Watchdog timer PCL clock output Mode register (WTM) Clock selection register (WDCS) Mode register (WDTM) Clock output selection register (CKS) Control register (SGCR) Sound generator Amplitude control (SGAM) Buzzer control (SGBC) Operating mode register (CSIM30, CSIM31) Shift register (SIO30, SIO31) Serial interface switch register (SIOSWI) Serial interface Asynchronous mode register (ASIM0) Asynchronous status register (ASIS0) Baudrate generator control register (BRGL0) 00H Transmit shift register (TXS0) Receive buffer register (RXB0) Mode register (ADM1) Conversion result register (ADCR1) A/D converter Input select register (ADS1) FFH 00H 00H 00H Power Fail Comparator Mode Register (PFM) 00H Power Fail Comparator Transload Register (PFT) LCD-controller/driver Mode register (LCDM) Control register (LCDC) Request flag register (IF0L, IF0H, IF1L) Mask flag register (MK0L, MK0H, MK1L) Interrupt Priority specify flag register (PR0L, PR0H, PR1L) External interrupt rising edge register (EGP) 00H 00H 00H 00H FFH FFH 00H External interrupt falling edge register (EGN) 00H Flash self-programming mode control register 08H (FLPMC) Self-programming and oscillation control reg08H ister (SPOC) Flash self-programming 384 User's Manual U16504EE1V1UD00 Chapter 22 Table 22-1: Hardware Reset Function Hardware Status after Reset (3/3) Status after Reset 01H 00H 00H 00H 00H 00H 00H 00H 3FH 18H 0EH 00H 00H 00H 00H 00H Control register (CANC) Transmit control register (TCR) Receive message register (RMES) Redefinition register (REDEF) Error status register (CANES) Transmit error counter register (TEC) CAN Receive error counter register (REC) Message count register (MCNT) Bit rate prescaler register (BRPRS) Synchronous control register (SYNC0) Synchronous control register (SYNC1) Mark control register (MASKC) Counter Register (SMCNT) PWM timer control register (MCNTC) Port mode control register 8 bit compare register (MCMP10, MCMP11, MCMP20, MCMP21, MCMP30, MCMP31, Stepper Motor controller/driver MCMP40, MCMP41) (Instrument C10) Compare control register (MCMPC1, MCMPC2, MCMPC3, MCMPC4) Meter controller/driver clock switch register (SMSWI) 00H 00H User's Manual U16504EE1V1UD00 385 [MEMO] 386 User's Manual U16504EE1V1UD00 Chapter 23 PD78F0828A and Memory Definition The flash memory versions of the PD780828A Subseries includes the PD78F0828A. The PD78F0828A replaces the internal mask ROM of the PD780828A with flash memory to which a program can be written, deleted and overwritten while mounted on the PCB. Table 23-1 lists the differences among the PD78F0828A and the mask ROM versions. Table 23-1: Differences among PD78F0828A and Mask ROM Versions Item PD78F0828A None Available Mask ROM Versions Available None IC pin VPP pin Electrical characteristics Please refer to Chapter 25 "Electrical Specifications" on page 411 of this document. Caution: Flash memory versions and mask ROM versions differ in their noise tolerance and noise emission. If replacing flash memory versions with mask ROM versions when changing from test production to mass production, be sure to perform sufficient evaluation with CS versions (not ES versions) of mask ROM versions. User's Manual U16504EE1V1UD00 387 Chapter 23 PD78F0828A and Memory Definition 23.1 Memory Size Switching Register (IMS) This register specifies the internal memory size by using the memory size switching register (IMS), so that the same memory map as on the mask ROM version can be achieved by using the flash device. IMS is set with an 8-bit memory manipulation instruction. RESET input sets this register to CFH. Caution: When later on a mask device of the PD780828A Subseries is selected, be sure to set the value for this mask device as specified in Table 23-2 to IMS. Other settings are prohibited. Figure 23-1: Memory Size Switching Register Format Symbol IMS 7 RAM2 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address After Reset R/W FFF0H CFH R/W ROM3 1 1 1 ROM2 0 1 1 ROM1 0 0 1 ROM0 0 0 1 Internal ROM size selection 32 K bytes 48 K bytes 60 K bytes Setting prohibited Other than above RAM2 1 RAM1 1 RAM0 0 Internal high-speed RAM size selection 1024 bytes Setting prohibited Other than above Notes: 1. The values to be set after reset depend on the product (See Table 23-2). 2. Even if the flash version has a memory size of 59.5 K flash memory, the register has to be set to a flash memory size of 60 K. Table 23-2: Values to be set after Reset for the Memory Size Switching Register Part Number PD780824B PD780826B PD780828B PD78F0828B Reset Value C8H CCH CFH CFH 388 User's Manual U16504EE1V1UD00 Chapter 23 PD78F0828A and Memory Definition 23.2 Internal Expansion RAM Size Switching Register The PD78F0828A allows users to define its internal extension RAM size by using the internal expansion RAM size switching register (IXS), so that the same memory mapping as that of a mask ROM version with a different internal expansion RAM is possible. The IXS is set by an 8-bit memory manipulation instruction. RESET signal input sets IXS to the value indicated in Table 23-4. Caution: When later on a mask device of the PD780828A Subseries is selected, be sure to set the value for this mask device as specified in Table 23-2 to IMS. Other settings are prohibited. Figure 23-2: Internal Expansion RAM Size Switching Register Format Symbol IXS 7 0 6 0 5 0 4 0 3 2 1 0 Address After Reset R/W FFF4H Note 1 IXRAM3 IXRAM2 IXRAM1 IXRAM0 R/W IXRAM3 1 1 IXRAM2 0 0 IXRAM1 1 0 IXRAM0 1 0 Internal Expansion RAM capacity selection 480 bytes 2016 bytes Setting prohibited Other than above Notes: 1. The values after Reset depend on the product (see Table 23-4). 2. The value which is set in the IXS that has the identical memory map to the mask ROM versions is given in Table 23-3. Table 23-3: Examples of internal Expansion RAM Size Switching Register Settings Relevant Mask ROM Version PD780824A PD780826A PD780828A PD78F0828A IXS Setting 0BH 0BH 08H 08H Table 23-4: Values when the Internal Expansion RAM Size Switching Register is Reset Part Number PD780824A PD780826A Reset Value 0CH 0CH 0CH 08H PD780828A PD78F0828A User's Manual U16504EE1V1UD00 389 Chapter 23 PD78F0828A and Memory Definition 23.3 Self-Programming and Oscillation Control Register The PD78F0828A allows users to reduce the power consumption in HALT mode by a selection of the clock supply of the flash memory. The SPOC register is set with an 8-bit memory manipulation instruction. RESET signal input sets SPOC to 08H. Figure 23-3: Self-Programming and Oscillation Control Register Format Symbol SPOC 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address After Reset R/W FF51H 08H R/W HCSEL1 HCSEL0 HCSEL1 0 0 1 1 HCSEL0 0 1 0 1 HALT Mode Clock Select fX/24 (500 KHz) fX/25 (250 KHz) fX/26 (125 KHz) fX/27 (62.5 KHz) 390 User's Manual U16504EE1V1UD00 Chapter 23 PD78F0828A and Memory Definition 23.4 Flash memory programming with flash programmer On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done after connecting a dedicated flash writer to the host machine and the target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to flash programmer. 23.4.1 Selection of transmission method Writing to flash memory is performed using flash programmer and serial communication. Select the transmission method for writing from Table 23-5. For the selection of the transmission method, a format like the one shown in Figure 23-4 is used. The transmission methods are selected with the VPP pulse numbers shown in Table 23-5. Table 23-5: Transmission Method 3-wire serial I/O (SIO30) 3-wire serial I/O (SIO30) with Handshake UART Transmission Method List Pin Used SI30/P37, SO30/P36, SCK30/P35 SI30/P37, SO30/P36, SCK30/P35, Handshake/P34 RXD0/P62, TXD0/P63 Number of VPP Pulses 0 3 8 Number of Channels 1 1 1 Cautions: 1. Be sure to select the number of VPP pulses shown in Table 23-5 for the transmission method. 2. If performing write operations to flash memory with the UART transmission method, set the main system clock oscillation frequency to 3 MHz or higher. Figure 23-4: Transmission Method Selection Format V PP pulses 10 V V PP VDD V SS VDD RESET VSS Flash write mode 23.4.2 Initialization of the programming mode When VPP reaches up to 10 V with RESET terminal activated, on-board programming mode becomes available. After release of RESET, the programming mode is selected by the number of VPP pulses. User's Manual U16504EE1V1UD00 391 Chapter 23 PD78F0828A and Memory Definition 23.4.3 Flash memory programming function Flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. The main functions are listed in Table 23-6. Table 23-6: Function Reset Chip verify Chip internal verify Chip blank check High-speed write Continuous write Chip pre-write Area verify Area internal verify Area erase Area write back Area blank check Area pre-write Oscillation frequency setting Erase time setting Baudrate setting Write back time setting Silicon signature read Main Functions of Flash Memory Programming Description Detects write stop and transmission synchronization Compares the entire memory contents and input data Compares the entire memory contents internally Checks the deletion status of the entire flash memory Performs writing to the flash memory according to the write start address and the number of write data (bytes) Performs successive write operations using the data input with highspeed write operation Performs the write operation with 00H to the entire flash memory Compares the entire flash area contents and input data Compares the entire flash area contents internally Erases the entire flash area Performs the write back function after the erase of the flash area Checks the deletion status of the entire flash area Performs the write operation with 00H to the entire flash area Inputs the resonator oscillation frequency information Defines the flash memory erase time Sets the transmission rate when the UART method is used Defines the flash memory write back time Outputs the device name, memory capacity, and device block information 392 User's Manual U16504EE1V1UD00 Chapter 23 PD78F0828A and Memory Definition 23.4.4 Flash programmer connection Connection of flash programmer and PD78F0828A differs depending on communication method (3-wire serial I/O, UART). Each case of connection shows in Figures 23-5, 23-6 and 23-7. Figure 23-5: Connection of using the 3-Wire SIO30 Method PD78F0828A VPP VDD RESET SCK30 SI30 SO30 VSS X1 Flash programmer VPP VDD RESET SCK SO SI GND CLK Figure 23-6: Connection of using the 3-Wire SIO30 Method with Handshake PD78F0828A VPP VDD RESET SCK30 SI30 SO30 P34 VSS X1 Flash programmer VPP VDD RESET SCK SO SI Reserved GND CLK User's Manual U16504EE1V1UD00 393 Chapter 23 Figure 23-7: Flash programmer VPP VDD RESET SO SI GND CLK PD78F0828A and Memory Definition Connection of using the UART Method PD78F0828A VPP VDD RESET RXD0 TXD0 VSS X1 VPP RESET System clock CLK, X1 : : : : Programming voltage applied from the on-board programming tool. A RESET is generated and the device is set to the on-board programming mode. The CPU clock for the device CLK may be supplied by the on-board program tool. Alternatively the crystal or ceramic oscillator on the target H/W can be used in the on-board programming mode. The external system clock has to be connected with the X1 pin on the device. The power supply for the device may be supplied by the on-board program tool. Alternatively the power supply on the target H/W can be used in the on-board programming mode. Ground level VSS. Serial clock generated by the on-board programming tool. Serial data sent by the on-board programming tool. Serial data sent by the device. Serial data sent by the on-board programming tool. Serial data sent by the device. Handshake line. VDD : GND SCK30 SI30 SO30 RXD TXD HS : : : : : : : 23.4.5 Flash programming precautions * Please make sure that the signals used by the on-board programming tool do not conflict with other devices on the target H/W. * A read functionality is not supported because of software protection. Only a verify operation of the whole Flash EPROM is supported. In verify mode data from start address to final address has to be supplied by the programming tool. The device compares each data with on-chip flash content and replies with a signal for O.K. or not O.K. 394 User's Manual U16504EE1V1UD00 Chapter 23 PD78F0828A and Memory Definition 23.5 Flash Self-Programming Control The PD78F0828A provides the secure self-programming with real-time support. further details are provided in an application note (U14995E). 23.5.1 Flash Self-Programming Mode Control Register The flash programming mode control register allows to enable/disable the self-programming mode of the PD78F0828A. The FLPMC register is set with an 8-bit memory manipulation instruction. RESET input sets FLPMC to 08H. Figure 23-8: Flash Self-Programming Mode Control Register Format Symbol FLPMC 7 0 6 0 5 0 4 0 3 1 2 VPP 1 0 0 FLSPM0 Address After Reset R/W FF50H 08H R/W VPP 0 1 No Yes Programming Voltage Detected FLSPM0 0 1 Self-Programming Mode Selection Normal operation mode Self-programming mode Remark: The bit VPP is a read-only flag. User's Manual U16504EE1V1UD00 395 [MEMO] 396 User's Manual U16504EE1V1UD00 Chapter 24 Instruction Set This chapter describes each instruction set of the PD780828A subseries as list table. For details of its operation and operation code, refer to the separate document "78K/0 series USER'S MANUAL - Instruction (U12326E)." 24.1 Legends Used in Operation List 24.1.1 Operand identifiers and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. Each symbol has the following meaning. * # : Immediate data specification *! : Absolute address specification * $ : Relative address specification * [ ] : Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $, and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 24-1: Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Operand Identifiers and Description Methods Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbolNote Special-function register symbol (16-bit manipulatable register even addresses only)Note FE20H-FF1FH Immediate data or labels FE20H-FF1FH Immediate data or labels (even address only) 0000H-FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions) 0800H-0FFFH Immediate data or labels 0040H-007FH Immediate data or labels (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3 Note: Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark: For special-function register symbols, refer to Table 3-5, "Special Function Register List," on page 67. User's Manual U16504EE1V1UD00 397 Chapter 24 24.1.2 Description of "operation" column A X B C D E H L AX BC DE HL PC SP PSW CY AC Z RBS IE () : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair : Program counter : Stack pointer : Program status word : Carry flag : Auxiliary carry flag : Zero flag : Register bank select flag : Interrupt request enable flag Instruction Set NMIS : Non-maskable interrupt servicing flag : Memory contents indicated by address or register contents in parentheses : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) ----: Inverted data addr16 : 16-bit immediate data or label jdisp8 : Signed 8-bit data (displacement value) XH, XL : Higher 8 bits and lower 8 bits of 16-bit register 25.1.3 Description of "flag operation" column (Blank) : Not affected 0 1 X R : Cleared to 0 : Set to 1 : Set/cleared according to the result : Previously saved value is restored 398 User's Manual U16504EE1V1UD00 Chapter 24 Instruction Set 24.2 Operation List Table 24-2: Instruction Mnemonic Group Operands r, #byte saddr, #byte sfr, #byte A, r Note 3 r, A Note 3 A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A MOV PSW, #byte A, PSW PSW, A A, [DE] 8-bit data transfer [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A A, [HL + B] [HL + B], A A, [HL + C] [HL + C], A A, r Note 3 A, saddr A, sfr A, !addr16 XCH A, [DE] A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Byte 2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1 1 2 2 3 1 1 2 2 2 Operation List (1/8) Clock Note 2 Note 1 Operation r byte (saddr) byte str byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) PSW byte A PSW PSW A A (DE) A (HL) A (HL + byte) A (HL + B) A HL + C) Ar A (saddr) A (sfr) Flag Z AC CY 4 6 2 2 4 4 8 8 4 4 4 4 8 8 6 6 6 6 2 4 8 4 4 8 8 8 7 7 5 5 5 5 9+n 7 5 5 5+n 5+n 9+n 7+n 7+n 6 6 9 + m (addr16) A x x x x x x 5 + m (DE) A 5 + m (HL) A 9 + m (HL + byte) A 7 + m (HL + B) A 7 + m (HL + C) A 10+n+m A (addr16) 6+n+m A (DE) 6+n+m A (HL) 10+n+m A (HL + byte) 10+n+m A (HL + B) 10+n+m A (HL + C) Notes: 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" 4. Only when rp = BC, DE or HL Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. User's Manual U16504EE1V1UD00 399 Chapter 24 Table 24-2: Instruction Mnemonic Group Operands rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX 16-bit data MOVW transfer AX, sfrp sfrp, AX AX, rp Note 4 Instruction Set Operation List (2/8) Clock Note 2 Byte 3 4 4 2 2 2 2 1 1 3 3 1 2 3 2 2 2 3 1 2 2 2 2 3 2 2 2 3 1 2 2 2 Note 1 Operation rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX Flag Z AC CY 6 8 6 6 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 10 10 8 8 8 8 - rp, AX Note 4 AX, !addr16 !addr16, AX XCHW AX, rp Note 4 A, #byte saddr, #byte A, r r, A ADD A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] 8-bit operation A, [HL + C] A, #byte saddr, #byte A, r r, A ADDC A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Note 3 12 + 2n AX (addr16) 12 + 2m (addr16) AX 8 5 9+n 5+n 9+n 9+n 9+n 8 5 9+n 5+n 9+n 9+n 9+n AX x rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r r, CY r + A A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + (HL + B) A, CY A + (HL + C) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY r, CY r + A + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A + (HL + B) + CY A, CY A + (HL + C) + CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes: 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" 4. Only when rp = BC, DE or HL Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 400 User's Manual U16504EE1V1UD00 Chapter 24 Instruction Set Table 24-2: Instruction Mnemonic Group Operands A, #byte saddr, #byte A, r r, A SUB A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A 8-bit operation SUBC A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A AND A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Note 3 Note 3 Operation List (3/8) Clock Note 2 Byte 2 3 2 2 2 3 1 2 2 2 2 3 2 2 2 3 1 2 2 2 2 3 2 2 2 3 1 2 2 2 Note 1 Operation A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r r, CY r - A A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - (HL + B) A, CY A - (HL + C) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY r, CY r - A - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A, CY A - (HL + B) - CY A, CY A - (HL + C) - CY A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) Flag Z AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 8 5 9+n 5+n 9+n 9+n 9+n 8 5 9+n 5+n 9+n 9+n 9+n 8 5 9+n 5+n 9+n 9+n 9+n Notes: 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" 4. Only when rp = BC, DE or HL Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. User's Manual U16504EE1V1UD00 401 Chapter 24 Table 24-2: Instruction Mnemonic Group Operands A, #byte saddr, #byte A, r r, A OR A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A 8-bit operation XOR A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A CMP A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] ADDW 16-bit operation Multiply/ divide SUBW CMPW MULU DIVUW AX, #word AX, #word AX, #word X C Note 3 Note 3 Note 3 Instruction Set Operation List (4/8) Clock Note 2 Byte 2 3 2 2 2 3 1 2 2 2 2 3 2 2 2 3 1 2 2 2 2 3 2 2 2 3 1 2 2 2 3 3 3 2 2 Note 1 Operation A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A - byte (saddr) - byte AA - r r-A A - (saddr) A - (addr16) A - (HL) A - (HL + byte) A - (HL + B) A - (HL + C) AX, CY AX + word AX, CY AX - word AX - word AX A x X AX (Quotient), C (Remainder) AX / C Flag Z AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 6 6 6 16 25 8 5 9+n 5+n 9+n 9+n 9+n 8 5 9+n 5+n 9+n 9+n 9+n 8 5 9+n 5+n 9+n 9+n 9+n - Notes: 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" 4. Only when rp = BC, DE or HL Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 402 User's Manual U16504EE1V1UD00 Chapter 24 Instruction Set Table 24-2: Instruction Mnemonic Group INC Increment/ DEC decrement INCW DECW ROR ROL RORC Rotate ROLC ROR4 ROL4 ADJBA BCD adjust ADJBS CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit MOV1 Bit manipulate CY, [HL].bit saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY CY, saddr.bit CY, sfr.bit AND1 CY, A.bit CY, PSW.bit CY, [HL].bit 2 3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 4 6 4 6 6 4 6 6 4 6 7 7 7 7+n 8 8 8 7 7 7 7+n r saddr r saddr rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL] 2 4 Operands Byte 1 2 1 2 1 1 1 1 1 1 2 Operation List (5/8) Clock Note 2 Note 1 Operation rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, (HL)3 - 0 (HL)7 - 4 A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 Decimal Adjust Accumulator after Addition Flag Z AC CY x x x x x x x x 2 4 2 4 4 4 2 2 2 2 10 6 6 12+n+m x x x x x x x x x x x x x x Decimal Adjust Accumulator after Subx tract CY saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY CY CY saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit x x x x x x x 8+n+m (HL).bit CY Notes: 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" 4. Only when rp = BC, DE or HL Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. User's Manual U16504EE1V1UD00 403 Chapter 24 Table 24-2: Instruction Mnemonic Group Operands CY, saddr.bit CY, sfr.bit OR1 CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit XOR1 CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit Bit manipulate SET1 sfr.bit A.bit PSW.bit [HL].bit saddr.bit sfr.bit CLR1 A.bit PSW.bit [HL].bit SET1 CLR1 NOT1 CY CY CY Byte 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1 Instruction Set Operation List (6/8) Clock Note 2 Note 1 Operation CY CY saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 CY 1 CY 0 CY CY Flag Z AC CY x x x x x x x x x x 6 4 6 6 4 6 4 4 6 4 4 6 2 2 2 7 7 7 7+n 7 7 7 7+n 6 8 6 6 8 6 - x x x 8+n+m (HL).bit 1 x x x 1 0 x 8+n+m (HL).bit 0 Notes: 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" 4. Only when rp = BC, DE or HL Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 404 User's Manual U16504EE1V1UD00 Chapter 24 Instruction Set Table 24-2: Instruction Mnemonic Group CALL Operands !addr16 Byte 3 Operation List (7/8) Clock Note 2 Note 1 Operation (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 PCH (SP + 1), PCL (SP),SP SP + 2 Flag Z AC CY 7 - CALLF !addr11 2 5 - CALLT Call/return BRK [addr5] 1 6 - 1 6 - RET RETI RETB PSW PUSH rp PSW Stack manipulate POP rp SP, #word MOVW SP, AX AX, SP Unconditional branch Conditional branch !addr16 BR BC BNC BZ BNZ $addr16 AX $addr16 $addr16 $addr16 $addr16 1 1 1 1 1 1 1 4 2 2 3 2 2 2 2 2 2 6 6 6 2 4 2 4 6 6 8 6 6 6 6 10 8 8 - PCH (SP + 1), PCL (SP), PSW R (SP + 2), SP SP + 3, NMIS 0 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP +2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 R R R R R R R R Notes: 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" 4. Only when rp = BC, DE or HL Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. User's Manual U16504EE1V1UD00 405 Chapter 24 Table 24-2: Instruction Mnemonic Group Operands saddr.bit, $addr16 sfr.bit, $addr16 BT A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 BF A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 saddr.bit, $addr16 Conditional branch BTCLR Byte 3 4 3 3 3 4 4 3 4 3 4 Instruction Set Operation List (8/8) Clock Note 2 Note 1 Operation PC PC + 3 + jdisp8 if(saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 4 + jdisp8 if(saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 PC PC + 4 + jdisp8 Flag Z AC CY 8 8 10 10 8 10 10 9 11 9 11 11 11 11 + n PC PC + 3 + jdisp8 if (HL).bit = 1 11 + n PC PC + 3 + jdisp8 if (HL).bit = 0 12 if(saddr.bit) = 1 then reset(saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit x x x sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 B, $addr16 DBNZ C, $addr16 saddr. $addr16 SEL NOP RBn 4 3 4 3 2 2 3 2 1 2 2 2 2 8 10 6 6 8 4 2 6 6 12 12 12+n+m PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit 10 6 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C C -1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if(saddr) 0 RBS1, 0 n No Operation IE 1(Enable Interrupt) IE 0(Disable Interrupt) Set HALT Mode Set STOP Mode CPU control EI DI HALT STOP Notes: 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" 4. Only when rp = BC, DE or HL Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 406 User's Manual U16504EE1V1UD00 Chapter 24 Instruction Set 24.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Table 24-3: 2nd Operand 1st Operand #byte A rNote sfr saddr !addr16 PSW [DE] [HL] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP 8-bit instructions [HL + byte] [HL + B] $addr16 [HL + C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB MOV SUBC AND OR XOR CMP MOV MOV MOV XCH XCH XCH ADD ADD ADD ADDC ADDC ADDC SUB MOV SUB SUB MOV MOV SUBC XCH SUBC SUBC XCH AND AND AND OR OR OR XOR XOR XOR CMP CMP CMP ROR ROL RORC ROLC r INC DEC B, C sfr MOV MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV MOV MOV MOV DBNZ saddr DBNZ INC DEC !addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] X C PUSH POP ROR4 ROL4 MOV MULU DIVU W Note: Except r = A User's Manual U16504EE1V1UD00 407 Chapter 24 (2) 16-bit instructions Instruction Set MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Table 24-4: 2nd Operand 1st Operand AX #word ADDW SUBW CMPW AX 16-bit instructions sfrp saddrp !addr16 sp None rpNote MOVW XCHW MOVW MOVW MOVW MOVW INCW DECW PUSH POP rp MOVW MOVW Note sfrp saddrp !addr16 sp MOVW MOVW MOVW MOVW MOVW MOVW MOVW Note: Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Table 24-5: 2nd Operand 1st Operand A.bit A.bit sfr.bit Bit manipulation instructions saddr.bit PSW.bit [HL].bit CY $addr16 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 MOV1 sfr.bit MOV1 saddr.bit MOV1 PSW.bit MOV1 [HL].bit MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 CY 408 User's Manual U16504EE1V1UD00 Chapter 24 Instruction Set (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Table 24-6: 2nd Operand 1st Operand Call/instructions/branch instructions AX !addr16 !addr11 [addr5] $addr16 BR BC BNC BZ BNZ BT BF BTCLR DBNZ Basic instruction BR CALL BR CALLF CALLT Compound instruction Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User's Manual U16504EE1V1UD00 409 [MEMO] 410 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications 25.1 Absolute Maximum Ratings (1) PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = 25C) Table 25-0: Parameter Symbol VDD VPP Supply voltage PD78F0828A(A) only Conditions Rating -0.3 to + 6.0 -0.3 to + 11.0 -0.3 to VDD + 0.3 -0.3 to + 0.3 -0.3 to + 6.0 -0.3 to + 0.3 P00 - P03, P34 - P37, P40 - P47, P60 - P65, P80 - P87, P90 - P97, X1, X2, RESET -0.3 to VDD +0.3 -0.3 to VDD +0.3 P10 to P14 P60 1 pin P20-P27 P20-P27 total High level output current IOH 1 pin P50-P57 P50-P57 total 1 pin except P60, P20-P27, P50-P57 P00 - P03, P34 - P37, P40 - P47, P61 - P65, P80 P87, P90 - P97, CTXD total P60 1 pin P20-P27 P20-P27 total Low level output current IOL 1 pin P50-P57 Note P50-P57 total 1 pin except P60, P20-P27, P50-P57 Peak Effective Peak Effective Peak Effective Peak Effective Peak Effective Peak Effective Analog input pin AVSS -0.3 to AVDD+0.3 -20 -35 -120 -80 -35 -120 -80 -10 -15 30 20 35 120 80 35 120 80 20 10 50 20 180 200 mA V (1/2) Unit AVDD/ AVDD = VDD AVREF AVSS SMVDD SMVDD = VDD, VDD = 5 V 10% SMVSS Input voltage Output voltage Analog input voltage VI1 VO VAN P00 - P03, P34 - P37, P40 - P47, P61 - Peak P65, P80 - P87, P90 - P97, CTXD total Effective PD780824A(A), Total through VDD, SMVDD PD780826A(A), PD780828A(A) and/or VSS, SMVSS PD78F0828A(A) Maximum current User's Manual U16504EE1V1UD00 411 Chapter 25 Electrical Specifications Table 25-0: (2/2) Unit Parameter Operating ambient temperature Storage temperature Symbol TA Conditions Rating -40 to +85 TSTG PD780824A(A), PD780826A(A), PD780828A(A) PD78F0828A(A) -65 to +150 -40 to +125 C Note: Effective value should be calculated as follows: [Effective value] = [Peak value] x duty Caution: Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily, because the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage. Therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. Remark: 412 User's Manual U16504EE1V1UD00 Chapter 25 (2) Electrical Specifications PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = 25C) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Symbol VDD AVDD/ AVDD = VDD AVREF Conditions Rating -0.3 to + 6.0 -0.3 to VDD + 0.3 -0.3 to + 0.3 -0.3 to + 6.0 -0.3 to + 0.3 Unit Supply voltage AVSS SMVDD SMVDD = VDD, VDD = 5 V 10% SMVSS V Input voltage Output voltage Analog input voltage High level output current VI1 VO VAN IOH P00 - P03, P34 - P37, P40 - P47, P60 - P65, P80 - P87, P90 - P97, X1, X2, RESET -0.3 to VDD +0.3 -0.3 to VDD +0.3 P10 to P14 1 pin Analog input pin AVSS -0.3 to AVDD+0.3 -10 -15 20 10 50 20 40 -40 to +110 C -65 to +150 mA P00 - P03, P20 - P27, P34 - P37, P40 - P47, P50 P57, P60 - P65, P80 - P87, P90 - P97, CTXD total 1 pin Peak Effective Low level output current IOLNote P00 - P03, P20 - P27, P34 - P37, P40 - Peak P47, P50 - P57, P60 - P65, P80 - P87, Effective P90 - P97, CTXD total Total through VDD, SMVDD and/or VSS, SMVSS Maximum current Operating ambient temperature Storage temperature TA TSTG Note: Effective value should be calculated as follows: [Effective value] = [Peak value] x duty Caution: Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily, because the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage. Therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. Remark: User's Manual U16504EE1V1UD00 413 Chapter 25 (3) Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = 25C) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Symbol VDD AVDD/ AVDD = VDD AVREF Conditions Rating -0.3 to + 6.0 -0.3 to VDD + 0.3 -0.3 to + 0.3 -0.3 to + 6.0 -0.3 to + 0.3 Unit Supply voltage AVSS SMVDD SMVDD = VDD, VDD = 5 V 10% SMVSS V Input voltage Output voltage Analog input voltage High level output current VI1 VO VAN IOH P00 - P03, P34 - P37, P40 - P47, P60 - P65, P80 - P87, P90 - P97, X1, X2, RESET -0.3 to VDD +0.3 -0.3 to VDD +0.3 P10 to P14 1 pin Analog input pin AVSS -0.3 to AVDD+0.3 -10 -15 20 10 50 20 40 -40 to +125 C -65 to +150 mA P00 - P03, P20 - P27, P34 - P37, P40 - P47, P50 P57, P60 - P65, P80 - P87, P90 - P97, CTXD total 1 pin Peak Effective Low level output current IOLNote P00 - P03, P20 - P27, P34 - P37, P40 - Peak P47, P50 - P57, P60 - P65, P80 - P87, Effective P90 - P97, CTXD total Total through VDD, SMVDD and/or VSS, SMVSS Maximum current Operating ambient temperature Storage temperature TA TSTG Note: Effective value should be calculated as follows: [Effective value] = [Peak value] x duty Caution: Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily, because the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage. Therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. Remark: 414 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications 25.2 Capacitance (1) PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = 25C, VDD = VSS = 0 V) Parameter Symbol Function f = 1 MHz Other than measured pins: 0 V P00 to P03, P34 to P37, P40 to P47, P61 to P65, P80 to P87, P90 to P97, f = 1 MHz Other than measured pins: 0 V CTXD P60, P20 to P27, P50 to P57 Min. Typ. Max. 15 Unit pF Input CIN capacitance Input/output CIO capacitance 15 pF 30 pF Remark: The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. (2) PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = 25C, VDD = VSS = 0 V) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Symbol Function f = 1 MHz Other than measured pins: 0 V P00 to P03, P34 to P37, P40 to P47, P61 to P65, P80 to P87, P90 to P97, f = 1 MHz Other than measured pins: 0 V CTXD P60, P20 to P27, P50 to P57 Min. Typ. Max. 15 Unit pF Input CIN capacitance Input/output CIO capacitance 15 pF 30 pF Remark: The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. User's Manual U16504EE1V1UD00 415 Chapter 25 (3) Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = 25C, VDD = VSS = 0 V) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Symbol Function f = 1 MHz Other than measured pins: 0 V P00 to P03, P34 to P37, P40 to P47, P61 to P65, P80 to P87, P90 to P97, f = 1 MHz Other than measured pins: 0 V CTXD P60, P20 to P27, P50 to P57 Min. Typ. Max. 15 Unit pF Input CIN capacitance Input/output CIO capacitance 15 pF 30 pF Remark: The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. 416 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications 25.3 Main System Clock Oscillation Circuit Characteristics (1) PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = -40C to +85C, VDD = 4.0 to 5.5 V) Resonator Recommended Circuit Parameter Oscillator frequency (fX) Note 1 Oscillation stabilization time Note 2 Conditions VDD = 4.0 to 5.5 V After VDD reaches oscillator voltage range MIN. 4.0 V VDD = 4.0 to 5.5 V After VDD reaches oscillator voltage range MIN. 4.0 V VDD = 4.0 to 5.5 V MIN. TYP. MAX. Unit 4.0 8.0 8.38 MHz IC X2 X1 Ceramic resonator C2 C1 10 ms IC X2 X1 Crystal resonator C2 C1 Oscillator frequency (fX) Note 1 Oscillation stabilization time Note 2 4.0 8.0 8.38 MHz 10 ms X2 X1 External clock X1 input frequency (fX) Note 1 4.0 8.0 8.38 MHz open PD74HCU04 X1 input high/low-level VDD = 4.0 to 5.5 V width (tXH, tXL) 55 125 ns Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution: When using the main system clock oscillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * * * * * * Wiring should be as short as possible. Wiring should not cross other signal lines. Wiring should not be placed close to a varying high current. The potential of the oscillation circuit capacitor ground should always be the same as that of VSS. Do not ground wiring to a ground pattern in which a high current flows. Do not fetch a signal from the oscillation circuit. User's Manual U16504EE1V1UD00 417 Chapter 25 (2) Electrical Specifications PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = -40C to +110C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Resonator Recommended Circuit Parameter Oscillator frequency (fX) Note 1 Oscillation stabilization time Note 2 Conditions VDD = 4.0 to 5.5 V After VDD reaches oscillator voltage range MIN. 4.0 V VDD = 4.0 to 5.5 V After VDD reaches oscillator voltage range MIN. 4.0 V VDD = 4.0 to 5.5 V MIN. TYP. MAX. Unit 4.0 8.0 8.38 MHz IC X2 X1 Ceramic resonator C2 C1 10 ms IC X2 X1 Crystal resonator C2 C1 Oscillator frequency (fX) Note 1 Oscillation stabilization time Note 2 4.0 8.0 8.38 MHz 10 ms X2 X1 External clock X1 input frequency (fX) Note 1 4.0 8.0 8.38 MHz open PD74HCU04 X1 input high/low-level VDD = 4.0 to 5.5 V width (tXH, tXL) 55 125 ns Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution: When using the main system clock oscillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * * * * * * Wiring should be as short as possible. Wiring should not cross other signal lines. Wiring should not be placed close to a varying high current. The potential of the oscillation circuit capacitor ground should always be the same as that of VSS. Do not ground wiring to a ground pattern in which a high current flows. Do not fetch a signal from the oscillation circuit. 418 User's Manual U16504EE1V1UD00 Chapter 25 (3) Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = -40C to +125C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Resonator Recommended Circuit Parameter Oscillator frequency (fX) Note 1 Oscillation stabilization time Note 2 Conditions VDD = 4.0 to 5.5 V After VDD reaches oscillator voltage range MIN. 4.0 V VDD = 4.0 to 5.5 V After VDD reaches oscillator voltage range MIN. 4.0 V VDD = 4.0 to 5.5 V MIN. TYP. MAX. Unit 4.0 8.0 8.38 MHz IC X2 X1 Ceramic resonator C2 C1 10 ms IC X2 X1 Crystal resonator C2 C1 Oscillator frequency (fX) Note 1 Oscillation stabilization time Note 2 4.0 8.0 8.38 MHz 10 ms X2 X1 External clock X1 input frequency (fX) Note 1 4.0 8.0 8.38 MHz open PD74HCU04 X1 input high/low-level VDD = 4.0 to 5.5 V width (tXH, tXL) 55 125 ns Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution: When using the main system clock oscillation circuit, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * * * * * * Wiring should be as short as possible. Wiring should not cross other signal lines. Wiring should not be placed close to a varying high current. The potential of the oscillation circuit capacitor ground should always be the same as that of VSS. Do not ground wiring to a ground pattern in which a high current flows. Do not fetch a signal from the oscillation circuit. User's Manual U16504EE1V1UD00 419 Chapter 25 Electrical Specifications 25.4 DC Characteristics (1) PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = -40C to +85C, VDD = 4.0 to 5.5 V) Table 25-0: Parameter Symbol VIH1 High-level input voltage VIH2 VIH4 Conditions P00 - P03, P10 - P14, P34 - P37, P40 - P47, P60 - P65, P80 - P87, P90 - P97, CRXD RESET X1, X2 P00 - P03, P10 - P14, P34 - P37, P40 - P47, P60 - P65, P80 - P87, P90 - P97, CRXD RESET X1, X2 P00 - P03, P34 - P37, P40 - P47, P60 - P67, P80 - P87, P90 - P97, CTXD P20 - P27, P50 - P57 VDD = 4.0 - 5.5 V IOH = -1 mA 0 MIN. 0.7 VDD 0.8 VDD VDD - 0.5 0 TYP. MAX. VDD VDD VDD 0.3 VDD 0.2 VDD 0.4 (1/2) Unit VIL1 Low-level input voltage VIL2 VIL4 VOH1 VDD - 1.0 High-level output voltage VOH2 4.5 V SMVDD 5.5 V IOH = -27 mA (TA = 85 C) IOH = -30 mA (TA = 25 C) IOH = -40 mA (TA = -40 C) VDD = 4.5 - 5.5 V IOH = -20 mA VDD = 4.0 - 5.5 V IOL = 1.6 mA VDD - 0.5 VDD -0.07 V VOH3 SGO P00 - P03, P34 - P37, P40 - P47, P60 - P67, P80 - P87, P90 - P97, CTXD P20 - P27, P50 - P57 VDD - 0.7 VOL1 0.4 Low-level output voltage VOL2 4.5 V SMVDD 5.5 V IOL = 27 mA (TA = 85 C) IOL = 30 mA (TA = 25 C) IOL = 40 mA (TA = -40 C) VDD = 4.5 - 5.5 V IOL = 20 mA 0.07 0.5 VOL3 SGO P00 - P03, P10 - P14, P20 - P27, P34 - P37, P40 - P47, P50 - P57, P60 - P67, P80 - P87, P90 - P97, RESET, CRXD, ANI10 -ANI14 X1, X2 P00 - P03, P10 - P14, P20 - P27, P34 - P37, P40 - P47, P50 - P57, P60 - P67, P80 - P87, P90 - P97, RESET, CRXD, ANI10 -ANI14 X1, X2 0.7 High-level input leakage current ILIH1 VIN = VDD 3 ILIH2 20 A Low-level input leakage current ILIL1 VIN = 0 V -3 IILIL2 -20 420 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications Table 25-0: (2/2) Unit Parameter High-level output leakage current Low-level output leakage current Software pull-up resistor Symbol ILOH ILOL R2 VOUT = VDD VOUT = 0 V VIN = 0 V Conditions MIN. TYP. MAX. 3 A -3 4.5 V VDD 5.5 V 10 30 100 K Remark: The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. User's Manual U16504EE1V1UD00 421 Chapter 25 Electrical Specifications PD780824A(A), PD780826A(A), PD780828A(A) Parameter Symbol Test Conditions fX = 8 MHz, crystal/ceramic oscillation operating mode (PCC = 00H) Note 2 fX = 8 MHz, crystal/ceramic oscillation operating mode (PCC = 00H) Note 3 fX = 8 MHz, crystal/ceramic oscillation HALT MIN. TYP. 5.5 MAX. 11 Unit IDD1 9.5 19 mA Power supply current Note 1 IDD2 mode (PCC = 04H) Note 4 fX = 8 MHz, crystal/ceramic oscillation HALT mode (PCC = 04H) Note 5 STOP mode 0.45 0.9 2.5 1 5 30 A IDD5 PD78F0828A(A) Parameter Symbol Test Conditions fX = 8 MHz, crystal/ceramic oscillation operating mode (PCC = 00H) Note 2 fX = 8 MHz, crystal/ceramic oscillation operating mode (PCC = 00H) Note 3 fX = 8 MHz, crystal/ceramic oscillation HALT MIN. TYP. 10.5 MAX. 21 Unit IDD1 16 32 mA Power supply current Note 1 IDD2 mode (PCC = 04H) Note 4 fX = 8 MHz, crystal/ceramic oscillation HALT mode (PCC = 04H) Note 5 STOP mode 0.6 1.2 2.7 1 5.5 30 A IDD5 Notes: 1. Current through VDD0, VDD1 respectively through VSS0, VSS1. Excluded is the current through the inside pull-up resistors, through AVDD/AVREF, the port current and the current for the LCD split resistors. 2. CPU is operable. The other peripherals like: CAN controller, stepper motor C/D, Timer 2, serial interfaces, sound generator and A/D converter are stopped. 3. CPU and all peripherals (except for the A/D converter) are in operating mode and PCL output is fX. 4. CPU is in HALT mode and all other peripherals (except watch timer) are stopped. 5. CPU is in HALT mode, but the following peripherals are active: Timer 2, all other timers, serial interfaces, and PCL output is fX. Remark: fX: Main system clock oscillation frequency. The typical values are with respect to TA = 25C. 422 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) LCD C/D 1/3 Bias Method Parameter LCD drive voltage LCD split resistor LCD output voltage deviation Note (common) LCD output voltage deviation Note (segment) Symbol VLCD RLCD Conditions MIN. 3.0 5 TYP. MAX. VDD Unit V K 15 45 VODC IO = 5 A 3.0 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD1 x 1/3 0 0.2 V VODS IO = 1 A 0 0.2 Note: The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCD). User's Manual U16504EE1V1UD00 423 Chapter 25 (2) Electrical Specifications PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = -40C to +110C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Table 25-0: Parameter Symbol VIH1 High-level input voltage VIH2 VIH4 VIL1 Low-level input voltage VIL2 VIL4 Conditions P00 - P03, P10 - P14, P34 - P37, P40 - P47, P60 - P65, P80 - P87, P90 - P97, CRXD RESET X1, X2 P00 - P03, P10 - P14, P34 - P37, P40 - P47, P60 - P65, P80 - P87, P90 - P97, CRXD RESET X1, X2 P00 - P03, P34 - P37, P40 - P47, P60 - P67, P80 - P87, P90 - P97, CTXD P20 - P27, P50 - P57 SGO P00 - P03, P34 - P37, P40 - P47, P60 - P67, P80 - P87, P90 - P97, CTXD P20 - P27, P50 - P57 SGO P00 - P03, P10 - P14, P20 - P27, P34 - P37, P40 - P47, P50 - P57, P60 - P67, P80 - P87, P90 - P97, RESET, CRXD, ANI10 -ANI14 X1, X2 P00 - P03, P10 - P14, P20 - P27, P34 - P37, P40 - P47, P50 - P57, P60 - P67, P80 - P87, P90 - P97, RESET, CRXD, ANI10 -ANI14 X1, X2 VDD = 4.0 - 5.5 V IOH = -1 mA 0 MIN. 0.7 VDD 0.8 VDD VDD - 0.5 0 TYP. MAX. VDD VDD VDD 0.3 VDD 0.2 VDD 0.4 (1/2) Unit VOH1 High-level output voltage VDD - 1.0 V VDD - 0.5 VDD - 0.7 VDD -0.07 VOH2 VOH3 4.5 V SMVDD 5.5 V IOH = -1 mA VDD = 4.5 - 5.5 V IOH = -1 mA VDD = 4.0 - 5.5 V IOL = 1.6 mA VOL1 Low-level output voltage 0.4 VOL2 VOL3 4.5 V SMVDD 5.5 V IOL = 1.6 mA VDD = 4.5 - 5.5 V IOL = 1.6 mA 0.07 0.4 0.4 High-level input leakage current ILIH1 10 VIN = VDD ILIH2 20 A Low-level input leakage current ILIL1 -10 VIN = 0 V IILIL2 -20 424 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications Table 25-0: (2/2) Unit Parameter High-level output leakage current Low-level output leakage current Software pull-up resistor Symbol ILOH ILOL R2 VOUT = VDD VOUT = 0 V VIN = 0 V Conditions MIN. TYP. MAX. 10 A -10 4.5 V VDD 5.5 V 10 30 100 K Remark: The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. User's Manual U16504EE1V1UD00 425 Chapter 25 Electrical Specifications PD780824A(A1), PD780826A(A1), PD780828A(A1) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Symbol Test Conditions fX = 8 MHz, crystal/ceramic oscillation operating mode (PCC = 00H) Note 2 fX = 8 MHz, crystal/ceramic oscillation operating mode (PCC = 00H) Note 3 fX = 8 MHz, crystal/ceramic oscillation HALT MIN. TYP. 5.5 MAX. 12 Unit IDD1 9.5 20 mA Power supply current Note 1 IDD2 mode (PCC = 04H) Note 4 fX = 8 MHz, crystal/ceramic oscillation HALT mode (PCC = 04H) Note 5 STOP mode 0.45 1.9 2.5 1 6 1000 A IDD5 Notes: 1. Current through VDD0, VDD1 respectively through VSS0, VSS1. Excluded is the current through the inside pull-up resistors, through AVDD/AVREF, the port current and the current for the LCD split resistors. 2. CPU is operable. The other peripherals like: CAN controller, stepper motor C/D, Timer 2, serial interfaces, sound generator and A/D converter are stopped. 3. CPU and all peripherals (except for the A/D converter) are in operating mode and PCL output is fX. 4. CPU is in HALT mode and all other peripherals (except watch timer) are stopped. 5. CPU is in HALT mode, but the following peripherals are active: Timer 2, all other timers, serial interfaces, and PCL output is fX. Remark: fX: Main system clock oscillation frequency. The typical values are with respect to TA = 25C. 426 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications PD780824A(A1), PD780826A(A1), PD780828A(A1) LCD C/D 1/3 Bias Method These specifications are only target values and may not be satisfied by mass-produced products. Parameter LCD drive voltage LCD split resistor LCD output voltage deviation Note (common) LCD output voltage deviation Note (segment) Symbol VLCD RLCD Conditions MIN. 3.0 5 TYP. MAX. VDD Unit V K 15 45 VODC IO = - 5 A 3.0 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD1 x 1/3 0 0.2 V VODS IO = - 1 A 0 0.2 Note: The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCD). Caution: The LCD-C/D cannot be used at high temperature (TA = 110C). The maximum temperature is TA = 85C. User's Manual U16504EE1V1UD00 427 Chapter 25 (3) Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = -40C to +125C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Table 25-0: Parameter Symbol VIH1 High-level input voltage VIH2 VIH4 Conditions P00 - P03, P10 - P14, P34 - P37, P40 - P47, P60 - P65, P80 - P87, P90 - P97, CRXD RESET X1, X2 P00 - P03, P10 - P14, P34 - P37, P40 - P47, P60 - P65, P80 - P87, P90 - P97, CRXD RESET X1, X2 P00 - P03, P34 - P37, P40 - P47, P60 - P67, P80 - P87, P90 - P97, CTXD P20 - P27, P50 - P57 SGO P00 - P03, P34 - P37, P40 - P47, P60 - P67, P80 - P87, P90 - P97, CTXD P20 - P27, P50 - P57 SGO P00 - P03, P10 - P14, P20 - P27, P34 - P37, P40 - P47, P50 - P57, P60 - P67, P80 - P87, P90 - P97, RESET, CRXD, ANI10 -ANI14 X1, X2 P00 - P03, P10 - P14, P20 - P27, P34 - P37, P40 - P47, P50 - P57, P60 - P67, P80 - P87, P90 - P97, RESET, CRXD, ANI10 -ANI14 X1, X2 VDD = 4.0 - 5.5 V IOH = -1 mA 0 MIN. 0.7 VDD 0.8 VDD VDD - 0.5 0 TYP. MAX. VDD VDD VDD 0.3 VDD 0.2 VDD 0.4 (1/2) Unit Low-level input voltage VIL1 VIL2 VIL4 VOH1 High-level output voltage VDD - 1.0 V VDD - 0.5 VDD - 0.7 VDD -0.07 VOH2 VOH3 4.5 V SMVDD 5.5 V IOH = -1 mA VDD = 4.5 - 5.5 V IOH = -1 mA VDD = 4.0 - 5.5 V IOL = 1.6 mA VOL1 Low-level output voltage 0.4 VOL2 VOL3 4.5 V SMVDD 5.5 V IOL = 1.6 mA VDD = 4.5 - 5.5 V IOL = 1.6 mA 0.07 0.4 0.4 High-level input leakage current ILIH1 10 VIN = VDD ILIH2 20 A Low-level input leakage current ILIL1 -10 VIN = 0 V IILIL2 -20 428 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications Table 25-0: (2/2) Unit Parameter High-level output leakage current Low-level output leakage current Software pull-up resistor Symbol ILOH ILOL R2 VOUT = VDD VOUT = 0 V VIN = 0 V Conditions MIN. TYP. MAX. 10 A -10 4.5 V VDD 5.5 V 10 30 100 K Remark: The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. User's Manual U16504EE1V1UD00 429 Chapter 25 Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Symbol Test Conditions fX = 8 MHz, crystal/ceramic oscillation operating mode (PCC = 00H) Note 2 fX = 8 MHz, crystal/ceramic oscillation operating mode (PCC = 00H) Note 3 fX = 8 MHz, crystal/ceramic oscillation HALT MIN. TYP. 5.5 MAX. 12 Unit IDD1 9.5 20 mA Power supply current Note 1 IDD2 mode (PCC = 04H) Note 4 fX = 8 MHz, crystal/ceramic oscillation HALT mode (PCC = 04H) Note 5 STOP mode 0.45 1.9 2.5 1 6 1000 A IDD5 Notes: 1. Current through VDD0, VDD1 respectively through VSS0, VSS1. Excluded is the current through the inside pull-up resistors, through AVDD/AVREF, the port current and the current for the LCD split resistors. 2. CPU is operable. The other peripherals like: CAN controller, stepper motor C/D, Timer 2, serial interfaces, sound generator and A/D converter are stopped. 3. CPU and all peripherals (except for the A/D converter) are in operating mode and PCL output is fX. 4. CPU is in HALT mode and all other peripherals (except watch timer) are stopped. 5. CPU is in HALT mode, but the following peripherals are active: Timer 2, all other timers, serial interfaces, and PCL output is fX. Remark: fX: Main system clock oscillation frequency. The typical values are with respect to TA = 25C. 430 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) LCD C/D 1/3 Bias Method These specifications are only target values and may not be satisfied by mass-produced products. Parameter LCD drive voltage LCD split resistor LCD output voltage deviation Note (common) LCD output voltage deviation Note (segment) Symbol VLCD RLCD Conditions MIN. 3.0 5 TYP. MAX. VDD Unit V K 15 45 VODC IO = - 5 A 3.0 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD1 x 1/3 0 0.2 V VODS IO = - 1 A 0 0.2 Note: The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCD). Caution: The LCD-C/D cannot be used at high temperature (TA = 125C). The maximum temperature is TA = 85C. User's Manual U16504EE1V1UD00 431 Chapter 25 Electrical Specifications 25.5 AC Characteristics 25.5.1 Basic Operation (1) PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = -40C to +85C, VDD = 4.0 to 5.5 V) Parameter Cycle time Note 1 TI50, TI51 input frequency TI50, TI51 input high/low level width TI20, TI21, TI22 input high/low level width Interrupt input high/low level width RESET low level width Symbol TCY fTI5 tTIH5 tTIL5 tTIH2 tTIL2 TINTH TINTL tRSL Test Conditions 4.0 V VDD 5.5 V MIN. 0.25 0 100 3/fSMP2 Note 2 TYP. MAX. 100 4 Unit s MHz ns INTP0-2 1 10 s Notes: 1. The cycle time equals to the minimum instruction execution time. For example: 1 NOP instruction corresponds to 2 CPU clock cycles (fCPU) selected by the processor clock control register (PCC). 2. fSMP2 (sampling clock) = fX/8, fX/16, fX/32, fX/64 TCY vs. VDD 60 10 Cycle time TCY [ s] Operation guaranteed range 2.0 1.0 0.5 0.4 0.25 0 1 2 3 4 5 6 Supply voltage VDD [V] 432 User's Manual U16504EE1V1UD00 Chapter 25 (2) Electrical Specifications PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = -40C to +110C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Cycle time Note 1 Symbol TCY fTI5 tTIH5 tTIL5 tTIH2 tTIL2 TINTH TINTL tRSL Test Conditions 4.0 V VDD 5.5 V MIN. 0.25 0 100 3/fSMP2 Note 2 TYP. MAX. 100 4 Unit s MHz ns TI50, TI51 input frequency TI50, TI51 input high/low level width TI20, TI21, TI22 input high/low level width Interrupt input high/low level width RESET low level width INTP0-2 1 10 s Notes: 1. The cycle time equals to the minimum instruction execution time. For example: 1 NOP instruction corresponds to 2 CPU clock cycles (fCPU) selected by the processor clock control register (PCC). 2. fSMP2 (sampling clock) = fX/8, fX/16, fX/32, fX/64 TCY vs. VDD 60 10 Cycle time TCY [ s] Operation guaranteed range 2.0 1.0 0.5 0.4 0.25 0 1 2 3 4 5 6 Supply voltage VDD [V] User's Manual U16504EE1V1UD00 433 Chapter 25 (3) Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = -40C to +125C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Cycle time Note 1 Symbol TCY fTI5 tTIH5 tTIL5 tTIH2 tTIL2 TINTH TINTL tRSL Test Conditions 4.0 V VDD 5.5 V MIN. 0.25 0 100 3/fSMP2 Note 2 TYP. MAX. 100 4 Unit s MHz ns TI50, TI51 input frequency TI50, TI51 input high/low level width TI20, TI21, TI22 input high/low level width Interrupt input high/low level width RESET low level width INTP0-2 1 10 s Notes: 1. The cycle time equals to the minimum instruction execution time. For example: 1 NOP instruction corresponds to 2 CPU clock cycles (fCPU) selected by the processor clock control register (PCC). 2. fSMP2 (sampling clock) = fX/8, fX/16, fX/32, fX/64 TCY vs. VDD 60 10 Cycle time TCY [ s] Operation guaranteed range 2.0 1.0 0.5 0.4 0.25 0 1 2 3 4 5 6 Supply voltage VDD [V] 434 User's Manual U16504EE1V1UD00 Chapter 25 25.5.2 Serial Interface (1) Electrical Specifications PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = -40C to +85C, VDD = 4.0 to 5.5 V) (a) Serial interface Channel CSI (SIO30) 3-wire serial I/O mode (SCK30 Internal clock output) Parameter SCK30 cycle time SCK30 high/low-level width SI30 setup time (to SCK30) SI30 hold time (from SCK30) SO30 output delay time (from SCK30) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 1000 tKCY1/2 - 50 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK30 output line 3-wire serial I/O mode (SCK30 External clock output) Parameter SCK30 cycle time SCK30 high/low-level width SI30 setup time (to SCK30) SI30 hold time (from SCK30) SO30 output delay time (from SCK30) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 800 400 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK30 output line User's Manual U16504EE1V1UD00 435 Chapter 25 Electrical Specifications (b) Serial interface Channel CSI (SIO31) 3-wire serial I/O mode (SCK31 Internal clock output) Parameter SCK31 cycle time SCK31 high/low-level width SI31 setup time (to SCK31) SI31 hold time (from SCK31) SO31 output delay time (from SCK31) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 1000 tKCY1/2 - 50 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK31 output line 3-wire serial I/O mode (SCK31 External clock output) Parameter SCK31 cycle time SCK31 high/low-level width SI31 setup time (to SCK31) SI31 hold time (from SCK31) SO31 output delay time (from SCK31) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 800 400 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK31 output line (c) Serial interface Channel UART UART mode (Dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 125 Unit Kbps 436 User's Manual U16504EE1V1UD00 Chapter 25 (2) Electrical Specifications PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = -40C to +110C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. (a) Serial interface Channel CSI (SIO30) 3-wire serial I/O mode (SCK30 Internal clock output) Parameter SCK30 cycle time SCK30 high/low-level width SI30 setup time (to SCK30) SI30 hold time (from SCK30) SO30 output delay time (from SCK30) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 1000 tKCY1/2 - 50 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK30 output line 3-wire serial I/O mode (SCK30 External clock output) Parameter SCK30 cycle time SCK30 high/low-level width SI30 setup time (to SCK30) SI30 hold time (from SCK30) SO30 output delay time (from SCK30) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 800 400 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK30 output line User's Manual U16504EE1V1UD00 437 Chapter 25 Electrical Specifications (b) Serial interface Channel CSI (SIO31) 3-wire serial I/O mode (SCK31 Internal clock output) Parameter SCK31 cycle time SCK31 high/low-level width SI31 setup time (to SCK31) SI31 hold time (from SCK31) SO31 output delay time (from SCK31) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 1000 tKCY1/2 - 50 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK31 output line 3-wire serial I/O mode (SCK31 External clock output) Parameter SCK31 cycle time SCK31 high/low-level width SI31 setup time (to SCK31) SI31 hold time (from SCK31) SO31 output delay time (from SCK31) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 800 400 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK31 output line (c) Serial interface Channel UART UART mode (Dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 125 Unit Kbps 438 User's Manual U16504EE1V1UD00 Chapter 25 (3) Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = -40C to +125C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. (a) Serial interface Channel CSI (SIO30) 3-wire serial I/O mode (SCK30 Internal clock output) Parameter SCK30 cycle time SCK30 high/low-level width SI30 setup time (to SCK30) SI30 hold time (from SCK30) SO30 output delay time (from SCK30) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 1000 tKCY1/2 - 50 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK30 output line 3-wire serial I/O mode (SCK30 External clock output) Parameter SCK30 cycle time SCK30 high/low-level width SI30 setup time (to SCK30) SI30 hold time (from SCK30) SO30 output delay time (from SCK30) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 800 400 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK30 output line User's Manual U16504EE1V1UD00 439 Chapter 25 Electrical Specifications (b) Serial interface Channel CSI (SIO31) 3-wire serial I/O mode (SCK31 Internal clock output) Parameter SCK31 cycle time SCK31 high/low-level width SI31 setup time (to SCK31) SI31 hold time (from SCK31) SO31 output delay time (from SCK31) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 1000 tKCY1/2 - 50 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK31 output line 3-wire serial I/O mode (SCK31 External clock output) Parameter SCK31 cycle time SCK31 high/low-level width SI31 setup time (to SCK31) SI31 hold time (from SCK31) SO31 output delay time (from SCK31) Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 800 400 100 400 MAX. Unit ns C = 100 pF Note 300 Note: C is the load capacitance of SO30, SCK31 output line (c) Serial interface Channel UART UART mode (Dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 125 Unit Kbps 440 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications AC Timing Test Points (excluding X1 Input) 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD Test points Clock Timing 1/fX tXL tXH VDD - 0.5 V 0.4 V X1 Input TI Timing tTILn TI20, TI21, TI22 TI50, TI51 tTIHn Remark: n = 2, 5 3-wire serial I/O mode / 2-wire serial I/O mode tKCYm tKLm tKHm SCK3n tSIKm tKSIm SI3n tKSO m Input data SO3n Output data Remark: m = 0, 1 User's Manual U16504EE1V1UD00 441 Chapter 25 25.5.3 Sound Generator Characteristics (1) Electrical Specifications PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = -40C to +85C, VDD = 4.0 to 5.5 V) Parameter Sound generator input frequency SGO output rise time SGO output fall time Symbol fSG1 fR fF Conditions MIN. TYP. MAX. 8.38 Unit MHz ns ns C=100 pFNote C=100 pFNote 80 80 200 200 (2) PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = -40C to +110C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Sound generator input frequency SGO output rise time SGO output fall time Symbol fSG1 fR fF Conditions MIN. TYP. MAX. 8.38 Unit MHz ns ns C=100 pFNote 80 80 200 200 C=100 pFNote (3) PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = -40C to +125C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Sound generator input frequency SGO output rise time SGO output fall time Symbol fSG1 fR fF Conditions MIN. TYP. MAX. 8.38 Unit MHz ns ns C=100 pFNote C=100 pFNote 80 80 200 200 Sound Generator Output Timing tR tF 0.9 VDD 0.1 VDD SGO 442 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications 25.5.4 Meter Controller / Driver Characteristics (1) PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = -40C to +85C, VDD = 4.0 to 5.5 V) Parameter Meter controller/driver input frequency PWM output rise time PWM output fall time Symbol fMCNote 1 fR fF HSPmn HSPmn Conditions MIN. TYP. MAX. 8.38 Unit MHz ns ns mV mV C=100 pFNote 2 C=100 pFNote 2 IOH = -27 mA HSPmn = I VOH [(SMmn)max - (SMmn)min] IOL = 27 mA HSPmn = I VOL[(SMmn)max - (SMmn)min] 80 80 200 200 50 50 Symmetry performanceNote 3 Notes: 1. Source clock of the free-running counter. 2. C is the load capacitance of the PWM output line. 3. Indicates the dispersion of 16 PWM output voltages. Remark: m = 1 to 4 n = 1 to 4 (2) PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = -40C to +110C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Meter controller/driver input frequency PWM output rise time PWM output fall time Symbol fMCNote 1 fR fF HSPmn HSPmn Conditions MIN. TYP. MAX. 8.38 Unit MHz ns ns mV mV C=100 pFNote 2 C=100 pFNote 2 IOH = -1 mA HSPmn = I VOH [(SMmn)max - (SMmn)min] IOL = 1 mA HSPmn = I VOL[(SMmn)max - (SMmn)min] 80 80 200 200 50 50 Symmetry performanceNote 3 Notes: 1. Source clock of the free-running counter. 2. C is the load capacitance of the PWM output line. 3. Indicates the dispersion of 16 PWM output voltages. Remark: m = 1 to 4, n = 1 to 4 The Meter C/D cannot be used at high temperature (TA = 110C). The maximum temperature is TA = 85C. User's Manual U16504EE1V1UD00 443 Chapter 25 Electrical Specifications (3) PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = -40C to +125C, VDD = 4.0 to 5.5 V) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Meter controller/driver input frequency PWM output rise time PWM output fall time Symbol fMCNote 1 fR fF HSPmn HSPmn Conditions MIN. TYP. MAX. 8.38 Unit MHz ns ns mV mV C=100 pFNote 2 C=100 pFNote 2 IOH = -1 mA HSPmn = I VOH [(SMmn)max - (SMmn)min] IOL = 1 mA HSPmn = I VOL[(SMmn)max - (SMmn)min] 80 80 200 200 50 50 Symmetry performanceNote 3 Notes: 1. Source clock of the free-running counter. 2. C is the load capacitance of the PWM output line. 3. Indicates the dispersion of 16 PWM output voltages. Remark: m = 1 to 4 n = 1 to 4 The Meter C/D cannot be used at high temperature (TA = 125C). The maximum temperature is TA = 85C. Meter Controller / Driver Output Timing tR tF 0.9 VDD 0.1 VDD SMmn 444 User's Manual U16504EE1V1UD00 Chapter 25 25.5.5 A/D Converter Characteristics (1) Electrical Specifications PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = -40C to +85C, VDD = 4.0 to 5.5 V, AVSS = VSS = 0V, fX = 8 MHz) Parameter Resolution Overall error Note Conversion time Analog input voltage Reference voltage AVDD / AVREF current Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 0.6 Unit bit % s tCONV VIAN AVDD / AVREF IREF AVDD = VDD ADCS-bit = 1 ADCS bit = 0 14 AVSS VDD VDD 750 0 AVDD VDD 1500 3 V A Note: Overall error excluding quantization ( 1/2 LSB). It is indicated as a ratio to the full-scale value. Remark: fX: Main system clock oscillation frequency. (2) PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = -40C to +110C, VDD = 4.0 to 5.5 V, AVSS = VSS = 0V, fX = 8 MHz) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Resolution Overall error Note Conversion time Analog input voltage Reference voltage AVDD / AVREF current Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 1.3 Unit bit % s tCONV VIAN AVDD / AVREF IREF AVDD = VDD ADCS-bit = 1 ADCS bit = 0 14 AVSS VDD VDD 750 0 AVDD VDD 1500 3 V A Note: Overall error excluding quantization ( 1/2 LSB). It is indicated as a ratio to the full-scale value. Remark: fX: Main system clock oscillation frequency. User's Manual U16504EE1V1UD00 445 Chapter 25 (3) Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = -40C to +125C, VDD = 4.0 to 5.5 V, AVSS = VSS = 0V, fX = 8 MHz) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Resolution Overall error Note Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 1.3 Unit bit % s Conversion time Analog input voltage Reference voltage AVDD / AVREF current tCONV VIAN AVDD / AVREF IREF AVDD = VDD ADCS-bit = 1 ADCS bit = 0 14 AVSS VDD VDD 750 0 AVDD VDD 1500 3 V A Note: Overall error excluding quantization ( 1/2 LSB). It is indicated as a ratio to the full-scale value. Remark: fX: Main system clock oscillation frequency. 446 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications 25.5.6 Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (1) PD780824A(A), PD780826A(A), PD780828A(A), PD78F0828A(A) (TA = -40C to +85C) Parameter Data retention power supply voltage Data retention power supply current Release signal set time Oscillation stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Test Conditions MIN. 2.5 TYP. MAX. 5.5 Unit V A s VDDDR = 4.0 V 0 Release by RESET Release by interrupt 1 30 217/fX Note ms Note: In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 212/fX and 214/fX to 217/fX is possible. Remark: fX: Main system clock oscillation frequency. (2) PD780824A(A1), PD780826A(A1), PD780828A(A1) (TA = -40C to +110C) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Data retention power supply voltage Data retention power supply current Release signal set time Oscillation stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Test Conditions MIN. 2.5 TYP. MAX. 5.5 Unit V A s VDDDR = 4.0 V 0 Release by RESET Release by interrupt 1 1000 217/fX Note ms Note: In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 212/fX and 214/fX to 217/fX is possible. Remark: fX: Main system clock oscillation frequency. User's Manual U16504EE1V1UD00 447 Chapter 25 (3) Electrical Specifications PD780824A(A2), PD780826A(A2), PD780828A(A2) (TA = -40C to +125C) These specifications are only target values and may not be satisfied by mass-produced products. Parameter Data retention power supply voltage Data retention power supply current Release signal set time Oscillation stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Test Conditions MIN. 2.5 TYP. MAX. 5.5 Unit V A s VDDDR = 4.0 V 0 Release by RESET Release by interrupt 1 1000 217/fX Note ms Note: In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 212/fX and 214/fX to 217/fX is possible. Remark: fX: Main system clock oscillation frequency. 448 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications Data Retention Timing (STOP mode release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retension mode VDD STOP instruction execution RESET VDDDR t SREL t WAIT Data Retention Timing (Standby release signal: STOP mode release by Interrupt signal) HALT mode STOP mode Operating mode Data retension mode VDD STOP instruction execution Standby release signal (interrupt request) VDDDR t SREL t WAIT Interrupt Input Timing t INTL t INTH INTP0 - INTP2 RESET Input Timing t RSEL RESET User's Manual U16504EE1V1UD00 449 Chapter 25 Electrical Specifications 25.5.7 Flash Memory Programming Characteristics: PD78F0828A(A) (TA = 10C to 40C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V, VPP = 9.7 to 10.3 V) (1) Basic characteristics Parameter Operating frequency Symbol fX VDD VPPL Conditions MIN. 4.0 4.0 TYP. MAX. 8.38 5.5 0.2 VDD Unit MHz V V V V Times When VPP low-level is detected When VPP high-level is detected When VPP high-voltage is detected and for programming 0 0.8 VDD 9.7 20Note 10 VDD 10.0 Supply voltage VPP VPPH 1.2 VDD 10.3 Number of rewrites Programming temperature CWRT tPRG +40 C Note: Operation is not guaranteed for over 20 rewrites. Remark: After execution of the program command, execute the verify command and check that the writing has been completed normally. (2) Serial write operation characteristics Parameter Set time from VDD to VPP Set time from VPP to RESET VPP count start time from RESET Count execution time VPP counter high-level width VPP counter low-level width VPP counter rise/fall time Symbol tDRPSR tPSRRF tRFCF tCOUNT tCH tCL tR, tF Conditions VPP high voltage VPP high voltage VPP high voltage MIN. 10 1.0 1.0 TYP. MAX. Unit s 2.0 8.0 8.0 Note Note ms s 1.0 Note: For maximum tCH / tCL, please make sure to finish the pulses within the time tCOUNT. 450 User's Manual U16504EE1V1UD00 Chapter 25 Electrical Specifications Flash Write Mode Setting Timing V DD 0V t DRPSR t RFCF VPPH VPP V DD VPPL V DD 0V t PSRRF t CL tF t COUNT tR t CH V DD RESET (input) User's Manual U16504EE1V1UD00 451 Chapter 25 (3) Write erase characteristics Electrical Specifications Parameter VPP supply voltage VDD supply current VPP supply current Step erase time Overall erase time per area Write-back time Number of write-backs per write-back command Number of erase/ write-backs Step write time Overall write time per word Number of rewrites per area Symbol VPP2 IDD IPP tER tERA tWB cWB cERWB tWR tWRW cERWR Note 5 Conditions During flash memory programming When VPP = 10 V, fX = 8.38 MHz When VPP = 10 V Note 1 MIN. 9.7 TYP. MAX. 10.0 10.3 50 100 0.2 Unit V mA mA s When step erase time = 0.2 s Note 3 Note 2 20 49.4 50 50.6 60 16 48 48 20 50 52 520 s/area ms Times/ write-back command Times s s/ word Times/ area When write-back time = 50 ms Note 4 When step write time = 50 s (1 word = 1 byte) Note 6 1 erase + 1 write after erase = = 1 rewrite Note 7 Notes: 1. The recommended setting value for the step erase time is 0.2 s. 2. The prewrite time before erasure and the erase verify time (write-back time) is not included. 3. The recommended setting value for the write-back time is 50 ms. 4. Write-back is executed once by the issuance of the write-back command. Therefore, the number of retries must be the maximum value minus the number of commands issued. 5. Recommended step write setting value is 50 s. 6. The actual write time per word is 100 s longer. The internal verify time during or after a write is not included. 7. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product P E P E P : 3 rewrites Shipped product E P E P E P : 3 rewrites Remarks: 1. The range of the operating clock during flash memory programming is the same as the range during normal operation. 2. When using the flashMASTER, the time parameters that need to be downloaded from the parameter files for write/erase are automatically set. Unless otherwise directed, do not change the set values. 452 User's Manual U16504EE1V1UD00 Chapter 26 Package Drawing 80 PIN PLASTIC QFP (14 x14) A B 60 61 41 40 detail of lead end C D S R Q 80 1 21 20 F G P H I M J K M N NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. INCHES 0.6770.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. P80GC-65-8BT Remark: The shape and material of the ES product is the same as the mass produced product. User's Manual U16504EE1V1UD00 453 [MEMO] 454 User's Manual U16504EE1V1UD00 Chapter 27 Recommended Soldering Conditions The PD780828A Subseries should be soldered and mounted under the conditions in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (IEI-1207). For soldering methods and conditions other than those recommended below, consult our sales personnel. * PD780824AGC(A)-XXX-8BT * PD780824AGC(A1)-XXX-8BT * PD780824AGC(A2)-XXX-8BT * PD780826AGC(A)-XXX-8BT * PD780826AGC(A1)-XXX-8BT * PD780826AGC(A2)-XXX-8BT * PD780828AGC(A)-XXX-8BT * PD780828AGC(A1)-XXX-8BT * PD780828AGC(A2)-XXX-8BT * PD78F0828AGC(A)-8BT : 80-pin plastic QFP (14 x 14 mm) : 80-pin plastic QFP (14 x 14 mm) : 80-pin plastic QFP (14 x 14 mm) : 80-pin plastic QFP (14 x 14 mm) : 80-pin plastic QFP (14 x 14 mm) : 80-pin plastic QFP (14 x 14 mm) : 80-pin plastic QFP (14 x 14 mm) : 80-pin plastic QFP (14 x 14 mm) : 80-pin plastic QFP (14 x 14 mm) : 80-pin plastic QFP (14 x 14 mm) Surface Mounting Type Soldering Conditions Soldering Method Soldering conditions Package peak temperature: 235C. Duration: 30 sec max. (at 210C or above). Number of times: twice max. Recommended Condition Symbol Infrared reflow IR35-00-2 VPS VR15-00-2 Wave soldering Pin part heating WS60-00-1 - Caution: Use of more than one soldering method should be avoided (except in the case of pin part heating). User's Manual U16504EE1V1UD00 455 [MEMO] 456 User's Manual U16504EE1V1UD00 Appendix A Development Tools The following development tools are available for the development of systems that employ the PD780828A Subseries. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products compatible with IBM PC/ATTM computers are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT computers. * Windows (Unless otherwise specified, "Windows" means the following OS). * Windows 95/98 * Windows NT Version 4.0 * Windows 2000 User's Manual U16504EE1V1UD00 457 Appendix A Figure A-1: Development Tools Development Tool Configuration (a) When using the in-circuit emulator IE-78K0-NS-A Language Processing Software * Assembler package * C compiler package * C library source file * Device file Debugging Tool * System simulator * Integrated debugger * Device file Embedded Software * Real-time OS * OS Host Machine (PC) Interface adapter, PC card interface, etc. Flash Memory Write Environment Flash programmer In-circuit Emulator Emulation board I/O board Power supply unit Flash memory write adapter Performance board On-chip flash memory version Emulation probe Conversion socket or conversion adapter Target system Remark: Items in broken line boxes differ according to the development environment. See A.3.1 Hardware. 458 User's Manual U16504EE1V1UD00 Appendix A Development Tools A.1 Language Processing Software NEC Software RA78K/0 Assembler Package This assembler converts programs written in mnemonics into an object codes executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with an optional device file. CC78K/0 C Compiler Package Device File CC78K/0-L C Library Source File IAR Software A78000 ICC78000 XLINK Assembler package used for the 78K0 series. C compiler package used for the 78K0 series. Linker package used for the 78K0 series. A.2 Flash Memory Writing Tools FlashMASTER Flashpro III (part number: FL-PR3, PG-FP3) Flash programmer dedicated to microcontrollers with on-chip flash memory. Flashpro IV (part number: PG-FP4) Flash Programmer FA-80GC-8BT Flash Memory Writing Adapter Flash memory writing adapter used connected to the Flashpro II and Flashpro III. * FA-80GC-8BT: 80-pin plastic QFP (GC-8BT type) User's Manual U16504EE1V1UD00 459 Appendix A Development Tools A.3 Debugging Tools A.3.1 Hardware (1) When using the In-Circuit Emulator IE-78K0-NS-A IE-78K0-NS-A In-circuit Emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to integrated debugger (ID78K0-NS). This emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. This adapter is used for supplying power from a receptacle of 100-V to 240-V AC. This adapter is used for supplying power from a receptable of 100 V to 240 V AC This adapter is required when using the PC-9800 series computer (except notebook type) as the IE-78K0-NS-A host machine (C bus compatible). This is PC card and interface cable required when using notebook-type computer as the IE-78K0-NS-A host machine (PCMCIA socket compatible). This adapter is required when using the IBM PC compatible computers as the IE78K0-NS-A host machine (ISA bus compatible). This adapter is required when using a computer with PCI bus as the IE-78K0-NS host machine. This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. This board provides the connection and buffers between the emulation board and the connector of the emulation probe. This probe is used to connect the in-circuit emulator to a target system and is designed for use with 80-pin plastic QFP (GC-8BT type). IE-70000-MC-PS-B Power Supply Unit EB-Power FW 7301/05 Power Supply Unit IE-70000-98-IF-C Interface Adapter IE-70000-CD-IF-A PC Card Interface IE-70000-PC-IF-C Interface Adapter IE-70000-PCI-IF-A Interface Adapter IE-78K0-NS-P04 Emulation Board IE-780828-NS-EM4 Probe Board NP-80GC-TQ Emulation Probe NQPACK080SB YQPACK080SB This conversion adapter connects the NP-80GC-TQ to a target system board YQSOCKET080SBF designed for a 80-pin plastic QFP (GC-8BT type). HQPACK080SB Conversion Adapter (2) Socket Details NQPACK080SB YQPACK080SB HQPACK080SB YQSOCKET080SBF Socket for soldering on the target. Adapter socket for connecting the probe to the NQPACK080SB Lid socket for connecting the device to the NQPACK080SB High adapter between the device to the YQPACK080SB and the probe 460 User's Manual U16504EE1V1UD00 Appendix A A.3.2 Software Development Tools SM78K0 System Simulator This system simulator is used to perform debugging at C source level or assembler level while simulating the operation of the target system on a host machine. This simulator runs on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. The SM78K0 should be used in combination with the optional device file. This debugger is a control program to debug 78K/0 Series microcontrollers. It adopts a graphical user interface, which is equivalent visually and operationally to Windows or OSF/MotifTM. It also has an enhanced debugging function for C ID78K0-NS language programs, and thus trace results can be displayed on screen in C-lanIntegrated Debugger guage level by using the windows integration function which links a trace result (supporting In-Circuit Emulator with its source program, disassembled display, and memory display. In addition, IE-78K0-NS-A) by incorporating function modules such as task debugger and system performance analyzer, the efficiency of debugging programs, which run on real-time OSs can be improved. It should be used in combination with the optional device file. User's Manual U16504EE1V1UD00 461 [MEMO] 462 User's Manual U16504EE1V1UD00 Appendix B Embedded Software For efficient development and maintenance of the PD780828A Subseries, the following embedded software products are available. B.1 Real-Time OS RX78K/0 Real-time OS MX78K0 OS RX78K/0 is a real-time OS conforming with the ITRON specifications. Tool (configurator) for generating nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K/0) and device file TRON specification subset OS. Nucleus of MX78K0 is supplied. This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next. Caution: When purchasing the RX78K/0, fill in the purchase application form in advance and sign the User Agreement. B.2 Fuzzy Inference Development Support System FE9000/FE9200 Fuzzy knowledge data creation tool Program that supports input, edit, and evaluation (simulation) of fuzzy knowledge data (fuzzy rule and membership function). FE9200 works on Windows. Part number: SxxxxFE9000 (PC-9800 Series) SxxxxFE9200 (IBM PC/AT and compatible machines) Program that translates fuzzy knowledge data obtained by using fuzzy knowledge. Translator data creation tool into assembler source program for RA78K0. Part number: SxxxxFT9080 (PC-9800 Series) SxxxxFT9085 (IBM PC/AT and compatible machines) Program that executes fuzzy inference. Executes fuzzy inference when linked with Fuzzy inference module, fuzzy knowledge data translated by translator. Part number: SxxxxFI78K0 (PC-9800 Series, IBM PC/AT and compatible machines) Support software for evaluation and adjustment of fuzzy knowledge data by using incircuit emulator and at hardware level. Part number: SxxxxFD78K0 (PC-9800 Series, PC/AT and compatible machines) FT9080/FT9085 FI78K0 FD78K0 Fuzzy inference debugger User's Manual U16504EE1V1UD00 463 [MEMO] 464 User's Manual U16504EE1V1UD00 Appendix C Index Numerics 16-bit timer mode control register (TMC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16-bit timer register (TM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8-bit timer mode control register 50 (TMC50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8-bit timer mode control register 51 (TMC51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8-bit timer registers 50 and 51 (TM50, TM51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 A A/D conversion result register (ADCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183, 194 A/D converter mode register (ADM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Analog input channel specification register (ADS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Asynchronous serial interface mode register (ASIM0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220, 226 Asynchronous serial interface status register (ASIS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222, 228 Auxiliary carry flag (AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 B Baud rate generator control register (BRGC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223, 229 Bit Rate Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 C CAN control register (CANC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 CAN Receive Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 CAN Transmit Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Capture pulse control register (CRC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Capture register 20 (CR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Capture register 21 (CR21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Capture register 22 (CR22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Carry flag (CY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Clock output selection register (CKS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Compare control register (MCMPCn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Compare register 50 and 51 (CR50, 51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Compare register n0 (MCMPn0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Compare register n1 (MCMPn1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 D D/A converter mode register (DAM0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DCAN Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 E External Interrupt Falling Edge Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 External interrupt rising edge enable register (EGP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 F Flash Self-Programming Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Free running up counter (SMCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 G General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I IDREC0 to IDREC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 IDTX0 to IDTX4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 In-service priority flag (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Internal Expansion RAM Size Switching Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Interrupt enable flag (IE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Interrupt mask flag registers (MK0L, MK0H, MK1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 User's Manual U16504EE1V1UD00 465 Appendix C Index Interrupt request flag (ADIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Interrupt request flag registers (IF0L, IF0H, IF1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 L LCD display control register (LCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 LCD display mode register (LCDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 LCD timer control register (LCDTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 M Mask control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Mask Identifier Control Register (MCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Memory Size Switching Register (IMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Message Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Meter controller/driver clock register (SMSWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 O Oscillation Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Oscillation Stabilization Time Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 P Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Port function register (PF3, PF4, PF8 and PF9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Port mode control register (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 port mode register (PM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 port mode register (PM9) 211, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Port mode register 3 (PM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Port mode register 6 (PM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Port mode register 9 (PM9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Port mode registers (PM0, PM2 to PM6, PM8, PM9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Power-fail compare mode register (PFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Power-fail compare threshold value register (PFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Prescaler mode register (PRM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Priority specify flag registers (PR0L, PR0H, PR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Processor clock control register (PCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Program status word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62, 360 Pull-up resistor option register (PU0, PU3, PU4, PU6, PU8, PU9) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Pulse width measurement with free-running counter and one capture register (TI20) . . . . . . . . . . . 119 R Receive buffer register (RXB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Receive message register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Receive shift register 1 (RXS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Redefinition control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Register bank select flags (RBS0 and RBS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 S Serial I/O shift register (SIO30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Serial I/O shift register (SIO31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Serial mode switch register (SIOSWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209, 212, 214 Serial Operation Mode Register (CSIM30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200, 201 466 User's Manual U16504EE1V1UD00 Appendix C Index Serial operation mode register (CSIM30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Serial Operation Mode Register (CSIM31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210, 211, 213 Serial operation mode register (CSIM31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Sound generator amplitude register (SGAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Sound generator buzzer control register (SGBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Sound generator control register (SGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Special function register (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66, 78 Special Function Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Successive approximation register (SAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Synchronization Control Registers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 T The serial I/O shift register (SIO31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Timer clock select register 50 (TCL50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Timer clock select register 51 (TCL51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Timer mode control register (MCNTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Transmit control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Transmit shift register 1 (TXS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 W Watch Timer Mode Register (WTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Watchdog timer clock select register (WDCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Watchdog timer mode register (WDTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Z Zero flag (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 User's Manual U16504EE1V1UD00 467 468 User's Manual U16504EE1V1UD00 Appendix D Revision History The following shows the revision history up to present. Application portions signifies the chapter of each edition. The Mark shows mayor revised points. Table 1-0: Edition No. EE1V1 Major items revised Correction of reference times in figure 9-2 (page 165) Caution (page 187) Description for the IMS register (page 388) Notes 1 (page 388) Description to Table 23-2 (page 388) Include Caution for IMS register (page 388) Notes 2 (page 389) Correction of Table 23-4 (page 389) Change of Conditions for VIH1, VIH2, VIL1, VIL2 (pages 420, 424, 428) 25.4 23.2 9.3 12.4 23.1 (1/2) Revised Sections User's Manual U16504EE1V1UD00 469 Appendix D Revision History Table 1-0: (2/2) Edition No. Major items revised Revised Sections 470 User's Manual U16504EE1V1UD00 Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Market Communication Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6465-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-6250-3583 Japan NEC Semiconductor Technical Hotline Fax: +81- 44-435-9608 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 99.1 Excellent Good Acceptable Poor |
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